1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2007-2013 ST-Ericsson 4*4882a593Smuzhiyun * DMA driver for COH 901 318 5*4882a593Smuzhiyun * Author: Per Friden <per.friden@stericsson.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef COH901318_H 9*4882a593Smuzhiyun #define COH901318_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MAX_DMA_PACKET_SIZE_SHIFT 11 12*4882a593Smuzhiyun #define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct device; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct coh901318_pool { 17*4882a593Smuzhiyun spinlock_t lock; 18*4882a593Smuzhiyun struct dma_pool *dmapool; 19*4882a593Smuzhiyun struct device *dev; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS 22*4882a593Smuzhiyun int debugfs_pool_counter; 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /** 27*4882a593Smuzhiyun * struct coh901318_lli - linked list item for DMAC 28*4882a593Smuzhiyun * @control: control settings for DMAC 29*4882a593Smuzhiyun * @src_addr: transfer source address 30*4882a593Smuzhiyun * @dst_addr: transfer destination address 31*4882a593Smuzhiyun * @link_addr: physical address to next lli 32*4882a593Smuzhiyun * @virt_link_addr: virtual address of next lli (only used by pool_free) 33*4882a593Smuzhiyun * @phy_this: physical address of current lli (only used by pool_free) 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun struct coh901318_lli { 36*4882a593Smuzhiyun u32 control; 37*4882a593Smuzhiyun dma_addr_t src_addr; 38*4882a593Smuzhiyun dma_addr_t dst_addr; 39*4882a593Smuzhiyun dma_addr_t link_addr; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun void *virt_link_addr; 42*4882a593Smuzhiyun dma_addr_t phy_this; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /** 46*4882a593Smuzhiyun * coh901318_pool_create() - Creates an dma pool for lli:s 47*4882a593Smuzhiyun * @pool: pool handle 48*4882a593Smuzhiyun * @dev: dma device 49*4882a593Smuzhiyun * @lli_nbr: number of lli:s in the pool 50*4882a593Smuzhiyun * @algin: address alignemtn of lli:s 51*4882a593Smuzhiyun * returns 0 on success otherwise none zero 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun int coh901318_pool_create(struct coh901318_pool *pool, 54*4882a593Smuzhiyun struct device *dev, 55*4882a593Smuzhiyun size_t lli_nbr, size_t align); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /** 58*4882a593Smuzhiyun * coh901318_pool_destroy() - Destroys the dma pool 59*4882a593Smuzhiyun * @pool: pool handle 60*4882a593Smuzhiyun * returns 0 on success otherwise none zero 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun int coh901318_pool_destroy(struct coh901318_pool *pool); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * coh901318_lli_alloc() - Allocates a linked list 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * @pool: pool handle 68*4882a593Smuzhiyun * @len: length to list 69*4882a593Smuzhiyun * return: none NULL if success otherwise NULL 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun struct coh901318_lli * 72*4882a593Smuzhiyun coh901318_lli_alloc(struct coh901318_pool *pool, 73*4882a593Smuzhiyun unsigned int len); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /** 76*4882a593Smuzhiyun * coh901318_lli_free() - Returns the linked list items to the pool 77*4882a593Smuzhiyun * @pool: pool handle 78*4882a593Smuzhiyun * @lli: reference to lli pointer to be freed 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun void coh901318_lli_free(struct coh901318_pool *pool, 81*4882a593Smuzhiyun struct coh901318_lli **lli); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /** 84*4882a593Smuzhiyun * coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy 85*4882a593Smuzhiyun * @pool: pool handle 86*4882a593Smuzhiyun * @lli: allocated lli 87*4882a593Smuzhiyun * @src: src address 88*4882a593Smuzhiyun * @size: transfer size 89*4882a593Smuzhiyun * @dst: destination address 90*4882a593Smuzhiyun * @ctrl_chained: ctrl for chained lli 91*4882a593Smuzhiyun * @ctrl_last: ctrl for the last lli 92*4882a593Smuzhiyun * returns number of CPU interrupts for the lli, negative on error. 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun int 95*4882a593Smuzhiyun coh901318_lli_fill_memcpy(struct coh901318_pool *pool, 96*4882a593Smuzhiyun struct coh901318_lli *lli, 97*4882a593Smuzhiyun dma_addr_t src, unsigned int size, 98*4882a593Smuzhiyun dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /** 101*4882a593Smuzhiyun * coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer 102*4882a593Smuzhiyun * @pool: pool handle 103*4882a593Smuzhiyun * @lli: allocated lli 104*4882a593Smuzhiyun * @buf: transfer buffer 105*4882a593Smuzhiyun * @size: transfer size 106*4882a593Smuzhiyun * @dev_addr: address of periphal 107*4882a593Smuzhiyun * @ctrl_chained: ctrl for chained lli 108*4882a593Smuzhiyun * @ctrl_last: ctrl for the last lli 109*4882a593Smuzhiyun * @dir: direction of transfer (to or from device) 110*4882a593Smuzhiyun * returns number of CPU interrupts for the lli, negative on error. 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun int 113*4882a593Smuzhiyun coh901318_lli_fill_single(struct coh901318_pool *pool, 114*4882a593Smuzhiyun struct coh901318_lli *lli, 115*4882a593Smuzhiyun dma_addr_t buf, unsigned int size, 116*4882a593Smuzhiyun dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last, 117*4882a593Smuzhiyun enum dma_transfer_direction dir); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /** 120*4882a593Smuzhiyun * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer 121*4882a593Smuzhiyun * @pool: pool handle 122*4882a593Smuzhiyun * @lli: allocated lli 123*4882a593Smuzhiyun * @sg: scatter gather list 124*4882a593Smuzhiyun * @nents: number of entries in sg 125*4882a593Smuzhiyun * @dev_addr: address of periphal 126*4882a593Smuzhiyun * @ctrl_chained: ctrl for chained lli 127*4882a593Smuzhiyun * @ctrl: ctrl of middle lli 128*4882a593Smuzhiyun * @ctrl_last: ctrl for the last lli 129*4882a593Smuzhiyun * @dir: direction of transfer (to or from device) 130*4882a593Smuzhiyun * @ctrl_irq_mask: ctrl mask for CPU interrupt 131*4882a593Smuzhiyun * returns number of CPU interrupts for the lli, negative on error. 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun int 134*4882a593Smuzhiyun coh901318_lli_fill_sg(struct coh901318_pool *pool, 135*4882a593Smuzhiyun struct coh901318_lli *lli, 136*4882a593Smuzhiyun struct scatterlist *sg, unsigned int nents, 137*4882a593Smuzhiyun dma_addr_t dev_addr, u32 ctrl_chained, 138*4882a593Smuzhiyun u32 ctrl, u32 ctrl_last, 139*4882a593Smuzhiyun enum dma_transfer_direction dir, u32 ctrl_irq_mask); 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* COH901318_H */ 142