1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Bestcomm ATA task microcode 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2004 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Created based on bestcom/code_dma/image_rtos1/dma_image.hex 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * The header consists of the following fields: 14*4882a593Smuzhiyun * u32 magic; 15*4882a593Smuzhiyun * u8 desc_size; 16*4882a593Smuzhiyun * u8 var_size; 17*4882a593Smuzhiyun * u8 inc_size; 18*4882a593Smuzhiyun * u8 first_var; 19*4882a593Smuzhiyun * u8 reserved[8]; 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * The size fields contain the number of 32-bit words. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun u32 bcom_ata_task[] = { 25*4882a593Smuzhiyun /* header */ 26*4882a593Smuzhiyun 0x4243544b, 27*4882a593Smuzhiyun 0x0e060709, 28*4882a593Smuzhiyun 0x00000000, 29*4882a593Smuzhiyun 0x00000000, 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Task descriptors */ 32*4882a593Smuzhiyun 0x8198009b, /* LCD: idx0 = var3; idx0 <= var2; idx0 += inc3 */ 33*4882a593Smuzhiyun 0x13e00c08, /* DRD1A: var3 = var1; FN=0 MORE init=31 WS=0 RS=0 */ 34*4882a593Smuzhiyun 0xb8000264, /* LCD: idx1 = *idx0, idx2 = var0; idx1 < var9; idx1 += inc4, idx2 += inc4 */ 35*4882a593Smuzhiyun 0x10000f00, /* DRD1A: var3 = idx0; FN=0 MORE init=0 WS=0 RS=0 */ 36*4882a593Smuzhiyun 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */ 37*4882a593Smuzhiyun 0x0c8cfc8a, /* DRD2B1: *idx2 = EU3(); EU3(*idx2,var10) */ 38*4882a593Smuzhiyun 0xd8988240, /* LCDEXT: idx1 = idx1; idx1 > var9; idx1 += inc0 */ 39*4882a593Smuzhiyun 0xf845e011, /* LCDEXT: idx2 = *(idx0 + var00000015); ; idx2 += inc2 */ 40*4882a593Smuzhiyun 0xb845e00a, /* LCD: idx3 = *(idx0 + var00000019); ; idx3 += inc1 */ 41*4882a593Smuzhiyun 0x0bfecf90, /* DRD1A: *idx3 = *idx2; FN=0 TFD init=31 WS=3 RS=3 */ 42*4882a593Smuzhiyun 0x9898802d, /* LCD: idx1 = idx1; idx1 once var0; idx1 += inc5 */ 43*4882a593Smuzhiyun 0x64000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 INT EXT init=0 WS=0 RS=0 */ 44*4882a593Smuzhiyun 0x0c0cf849, /* DRD2B1: *idx0 = EU3(); EU3(idx1,var9) */ 45*4882a593Smuzhiyun 0x000001f8, /* NOP */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* VAR[9]-VAR[14] */ 48*4882a593Smuzhiyun 0x40000000, 49*4882a593Smuzhiyun 0x7fff7fff, 50*4882a593Smuzhiyun 0x00000000, 51*4882a593Smuzhiyun 0x00000000, 52*4882a593Smuzhiyun 0x00000000, 53*4882a593Smuzhiyun 0x00000000, 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* INC[0]-INC[6] */ 56*4882a593Smuzhiyun 0x40000000, 57*4882a593Smuzhiyun 0xe0000000, 58*4882a593Smuzhiyun 0xe0000000, 59*4882a593Smuzhiyun 0xa000000c, 60*4882a593Smuzhiyun 0x20000000, 61*4882a593Smuzhiyun 0x00000000, 62*4882a593Smuzhiyun 0x00000000, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65