1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunmenuconfig PM_DEVFREQ 3*4882a593Smuzhiyun bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support" 4*4882a593Smuzhiyun select SRCU 5*4882a593Smuzhiyun select PM_OPP 6*4882a593Smuzhiyun help 7*4882a593Smuzhiyun A device may have a list of frequencies and voltages available. 8*4882a593Smuzhiyun devfreq, a generic DVFS framework can be registered for a device 9*4882a593Smuzhiyun in order to let the governor provided to devfreq choose an 10*4882a593Smuzhiyun operating frequency based on the device driver's policy. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun Each device may have its own governor and policy. Devfreq can 13*4882a593Smuzhiyun reevaluate the device state periodically and/or based on the 14*4882a593Smuzhiyun notification to "nb", a notifier block, of devfreq. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun Like some CPUs with CPUfreq, a device may have multiple clocks. 17*4882a593Smuzhiyun However, because the clock frequencies of a single device are 18*4882a593Smuzhiyun determined by the single device's state, an instance of devfreq 19*4882a593Smuzhiyun is attached to a single device and returns a "representative" 20*4882a593Smuzhiyun clock frequency of the device, which is also attached 21*4882a593Smuzhiyun to a device by 1-to-1. The device registering devfreq takes the 22*4882a593Smuzhiyun responsibility to "interpret" the representative frequency and 23*4882a593Smuzhiyun to set its every clock accordingly with the "target" callback 24*4882a593Smuzhiyun given to devfreq. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun When OPP is used with the devfreq device, it is recommended to 27*4882a593Smuzhiyun register devfreq's nb to the OPP's notifier head. If OPP is 28*4882a593Smuzhiyun used with the devfreq device, you may use OPP helper 29*4882a593Smuzhiyun functions defined in devfreq.h. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunif PM_DEVFREQ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyuncomment "DEVFREQ Governors" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig DEVFREQ_GOV_SIMPLE_ONDEMAND 36*4882a593Smuzhiyun tristate "Simple Ondemand" 37*4882a593Smuzhiyun help 38*4882a593Smuzhiyun Chooses frequency based on the recent load on the device. Works 39*4882a593Smuzhiyun similar as ONDEMAND governor of CPUFREQ does. A device with 40*4882a593Smuzhiyun Simple-Ondemand should be able to provide busy/total counter 41*4882a593Smuzhiyun values that imply the usage rate. A device may provide tuned 42*4882a593Smuzhiyun values to the governor with data field at devfreq_add_device(). 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunconfig DEVFREQ_GOV_PERFORMANCE 45*4882a593Smuzhiyun tristate "Performance" 46*4882a593Smuzhiyun help 47*4882a593Smuzhiyun Sets the frequency at the maximum available frequency. 48*4882a593Smuzhiyun This governor always returns UINT_MAX as frequency so that 49*4882a593Smuzhiyun the DEVFREQ framework returns the highest frequency available 50*4882a593Smuzhiyun at any time. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunconfig DEVFREQ_GOV_POWERSAVE 53*4882a593Smuzhiyun tristate "Powersave" 54*4882a593Smuzhiyun help 55*4882a593Smuzhiyun Sets the frequency at the minimum available frequency. 56*4882a593Smuzhiyun This governor always returns 0 as frequency so that 57*4882a593Smuzhiyun the DEVFREQ framework returns the lowest frequency available 58*4882a593Smuzhiyun at any time. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunconfig DEVFREQ_GOV_USERSPACE 61*4882a593Smuzhiyun tristate "Userspace" 62*4882a593Smuzhiyun help 63*4882a593Smuzhiyun Sets the frequency at the user specified one. 64*4882a593Smuzhiyun This governor returns the user configured frequency if there 65*4882a593Smuzhiyun has been an input to /sys/devices/.../power/devfreq_set_freq. 66*4882a593Smuzhiyun Otherwise, the governor does not change the frequency 67*4882a593Smuzhiyun given at the initialization. 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunconfig DEVFREQ_GOV_PASSIVE 70*4882a593Smuzhiyun tristate "Passive" 71*4882a593Smuzhiyun help 72*4882a593Smuzhiyun Sets the frequency based on the frequency of its parent devfreq 73*4882a593Smuzhiyun device. This governor does not change the frequency by itself 74*4882a593Smuzhiyun through sysfs entries. The passive governor recommends that 75*4882a593Smuzhiyun devfreq device uses the OPP table to get the frequency/voltage. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyuncomment "DEVFREQ Drivers" 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunconfig ARM_EXYNOS_BUS_DEVFREQ 80*4882a593Smuzhiyun tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver" 81*4882a593Smuzhiyun depends on ARCH_EXYNOS || COMPILE_TEST 82*4882a593Smuzhiyun select DEVFREQ_GOV_SIMPLE_ONDEMAND 83*4882a593Smuzhiyun select DEVFREQ_GOV_PASSIVE 84*4882a593Smuzhiyun select DEVFREQ_EVENT_EXYNOS_PPMU 85*4882a593Smuzhiyun select PM_DEVFREQ_EVENT 86*4882a593Smuzhiyun help 87*4882a593Smuzhiyun This adds the common DEVFREQ driver for Exynos Memory bus. Exynos 88*4882a593Smuzhiyun Memory bus has one more group of memory bus (e.g, MIF and INT block). 89*4882a593Smuzhiyun Each memory bus group could contain many memoby bus block. It reads 90*4882a593Smuzhiyun PPMU counters of memory controllers by using DEVFREQ-event device 91*4882a593Smuzhiyun and adjusts the operating frequencies and voltages with OPP support. 92*4882a593Smuzhiyun This does not yet operate with optimal voltages. 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunconfig ARM_IMX_BUS_DEVFREQ 95*4882a593Smuzhiyun tristate "i.MX Generic Bus DEVFREQ Driver" 96*4882a593Smuzhiyun depends on ARCH_MXC || COMPILE_TEST 97*4882a593Smuzhiyun select DEVFREQ_GOV_USERSPACE 98*4882a593Smuzhiyun help 99*4882a593Smuzhiyun This adds the generic DEVFREQ driver for i.MX interconnects. It 100*4882a593Smuzhiyun allows adjusting NIC/NOC frequency. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunconfig ARM_IMX8M_DDRC_DEVFREQ 103*4882a593Smuzhiyun tristate "i.MX8M DDRC DEVFREQ Driver" 104*4882a593Smuzhiyun depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \ 105*4882a593Smuzhiyun (COMPILE_TEST && HAVE_ARM_SMCCC) 106*4882a593Smuzhiyun select DEVFREQ_GOV_SIMPLE_ONDEMAND 107*4882a593Smuzhiyun select DEVFREQ_GOV_USERSPACE 108*4882a593Smuzhiyun help 109*4882a593Smuzhiyun This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows 110*4882a593Smuzhiyun adjusting DRAM frequency. 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunconfig ARM_TEGRA_DEVFREQ 113*4882a593Smuzhiyun tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver" 114*4882a593Smuzhiyun depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \ 115*4882a593Smuzhiyun ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \ 116*4882a593Smuzhiyun ARCH_TEGRA_210_SOC || \ 117*4882a593Smuzhiyun COMPILE_TEST 118*4882a593Smuzhiyun depends on COMMON_CLK 119*4882a593Smuzhiyun help 120*4882a593Smuzhiyun This adds the DEVFREQ driver for the Tegra family of SoCs. 121*4882a593Smuzhiyun It reads ACTMON counters of memory controllers and adjusts the 122*4882a593Smuzhiyun operating frequencies and voltages with OPP support. 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunconfig ARM_TEGRA20_DEVFREQ 125*4882a593Smuzhiyun tristate "NVIDIA Tegra20 DEVFREQ Driver" 126*4882a593Smuzhiyun depends on (TEGRA_MC && TEGRA20_EMC) || COMPILE_TEST 127*4882a593Smuzhiyun depends on COMMON_CLK 128*4882a593Smuzhiyun select DEVFREQ_GOV_SIMPLE_ONDEMAND 129*4882a593Smuzhiyun help 130*4882a593Smuzhiyun This adds the DEVFREQ driver for the Tegra20 family of SoCs. 131*4882a593Smuzhiyun It reads Memory Controller counters and adjusts the operating 132*4882a593Smuzhiyun frequencies and voltages with OPP support. 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunconfig ARM_ROCKCHIP_BUS_DEVFREQ 135*4882a593Smuzhiyun tristate "ARM ROCKCHIP BUS DEVFREQ Driver" 136*4882a593Smuzhiyun depends on ARCH_ROCKCHIP 137*4882a593Smuzhiyun help 138*4882a593Smuzhiyun This adds the DEVFREQ driver for the ROCKCHIP BUS. 139*4882a593Smuzhiyun 140*4882a593Smuzhiyunconfig ARM_ROCKCHIP_DMC_DEVFREQ 141*4882a593Smuzhiyun tristate "ARM ROCKCHIP DMC DEVFREQ Driver" 142*4882a593Smuzhiyun depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ 143*4882a593Smuzhiyun (COMPILE_TEST && HAVE_ARM_SMCCC) 144*4882a593Smuzhiyun select DEVFREQ_EVENT_ROCKCHIP_DFI 145*4882a593Smuzhiyun select PM_DEVFREQ_EVENT 146*4882a593Smuzhiyun help 147*4882a593Smuzhiyun This adds the DEVFREQ driver for the ROCKCHIP DMC(Dynamic Memory Controller). 148*4882a593Smuzhiyun It sets the frequency for the memory controller and reads the usage counts 149*4882a593Smuzhiyun from hardware. 150*4882a593Smuzhiyun 151*4882a593Smuzhiyunsource "drivers/devfreq/event/Kconfig" 152*4882a593Smuzhiyun 153*4882a593Smuzhiyunendif # PM_DEVFREQ 154