1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /** 3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2010 4*4882a593Smuzhiyun * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson. 5*4882a593Smuzhiyun * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson. 6*4882a593Smuzhiyun * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson. 7*4882a593Smuzhiyun * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson. 8*4882a593Smuzhiyun * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CRYP_P_H_ 12*4882a593Smuzhiyun #define _CRYP_P_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/io.h> 15*4882a593Smuzhiyun #include <linux/bitops.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "cryp.h" 18*4882a593Smuzhiyun #include "cryp_irqp.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /** 21*4882a593Smuzhiyun * Generic Macros 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define CRYP_SET_BITS(reg_name, mask) \ 24*4882a593Smuzhiyun writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CRYP_WRITE_BIT(reg_name, val, mask) \ 27*4882a593Smuzhiyun writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\ 28*4882a593Smuzhiyun ((val) & (mask))), reg_name) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CRYP_TEST_BITS(reg_name, val) \ 31*4882a593Smuzhiyun (readl_relaxed(reg_name) & (val)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CRYP_PUT_BITS(reg, val, shift, mask) \ 34*4882a593Smuzhiyun writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \ 35*4882a593Smuzhiyun (((u32)val << shift) & (mask))), reg) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * CRYP specific Macros 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define CRYP_PERIPHERAL_ID0 0xE3 41*4882a593Smuzhiyun #define CRYP_PERIPHERAL_ID1 0x05 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CRYP_PERIPHERAL_ID2_DB8500 0x28 44*4882a593Smuzhiyun #define CRYP_PERIPHERAL_ID3 0x00 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CRYP_PCELL_ID0 0x0D 47*4882a593Smuzhiyun #define CRYP_PCELL_ID1 0xF0 48*4882a593Smuzhiyun #define CRYP_PCELL_ID2 0x05 49*4882a593Smuzhiyun #define CRYP_PCELL_ID3 0xB1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /** 52*4882a593Smuzhiyun * CRYP register default values 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define MAX_DEVICE_SUPPORT 2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Priv set, keyrden set and datatype 8bits swapped set as default. */ 57*4882a593Smuzhiyun #define CRYP_CR_DEFAULT 0x0482 58*4882a593Smuzhiyun #define CRYP_DMACR_DEFAULT 0x0 59*4882a593Smuzhiyun #define CRYP_IMSC_DEFAULT 0x0 60*4882a593Smuzhiyun #define CRYP_DIN_DEFAULT 0x0 61*4882a593Smuzhiyun #define CRYP_DOUT_DEFAULT 0x0 62*4882a593Smuzhiyun #define CRYP_KEY_DEFAULT 0x0 63*4882a593Smuzhiyun #define CRYP_INIT_VECT_DEFAULT 0x0 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /** 66*4882a593Smuzhiyun * CRYP Control register specific mask 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun #define CRYP_CR_SECURE_MASK BIT(0) 69*4882a593Smuzhiyun #define CRYP_CR_PRLG_MASK BIT(1) 70*4882a593Smuzhiyun #define CRYP_CR_ALGODIR_MASK BIT(2) 71*4882a593Smuzhiyun #define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3)) 72*4882a593Smuzhiyun #define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6)) 73*4882a593Smuzhiyun #define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8)) 74*4882a593Smuzhiyun #define CRYP_CR_KEYRDEN_MASK BIT(10) 75*4882a593Smuzhiyun #define CRYP_CR_KSE_MASK BIT(11) 76*4882a593Smuzhiyun #define CRYP_CR_START_MASK BIT(12) 77*4882a593Smuzhiyun #define CRYP_CR_INIT_MASK BIT(13) 78*4882a593Smuzhiyun #define CRYP_CR_FFLUSH_MASK BIT(14) 79*4882a593Smuzhiyun #define CRYP_CR_CRYPEN_MASK BIT(15) 80*4882a593Smuzhiyun #define CRYP_CR_CONTEXT_SAVE_MASK (CRYP_CR_SECURE_MASK |\ 81*4882a593Smuzhiyun CRYP_CR_PRLG_MASK |\ 82*4882a593Smuzhiyun CRYP_CR_ALGODIR_MASK |\ 83*4882a593Smuzhiyun CRYP_CR_ALGOMODE_MASK |\ 84*4882a593Smuzhiyun CRYP_CR_DATATYPE_MASK |\ 85*4882a593Smuzhiyun CRYP_CR_KEYSIZE_MASK |\ 86*4882a593Smuzhiyun CRYP_CR_KEYRDEN_MASK |\ 87*4882a593Smuzhiyun CRYP_CR_DATATYPE_MASK) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define CRYP_SR_INFIFO_READY_MASK (BIT(0) | BIT(1)) 91*4882a593Smuzhiyun #define CRYP_SR_IFEM_MASK BIT(0) 92*4882a593Smuzhiyun #define CRYP_SR_BUSY_MASK BIT(4) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /** 95*4882a593Smuzhiyun * Bit position used while setting bits in register 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define CRYP_CR_PRLG_POS 1 98*4882a593Smuzhiyun #define CRYP_CR_ALGODIR_POS 2 99*4882a593Smuzhiyun #define CRYP_CR_ALGOMODE_POS 3 100*4882a593Smuzhiyun #define CRYP_CR_DATATYPE_POS 6 101*4882a593Smuzhiyun #define CRYP_CR_KEYSIZE_POS 8 102*4882a593Smuzhiyun #define CRYP_CR_KEYRDEN_POS 10 103*4882a593Smuzhiyun #define CRYP_CR_KSE_POS 11 104*4882a593Smuzhiyun #define CRYP_CR_START_POS 12 105*4882a593Smuzhiyun #define CRYP_CR_INIT_POS 13 106*4882a593Smuzhiyun #define CRYP_CR_CRYPEN_POS 15 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CRYP_SR_BUSY_POS 4 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /** 111*4882a593Smuzhiyun * CRYP PCRs------PC_NAND control register 112*4882a593Smuzhiyun * BIT_MASK 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun #define CRYP_DMA_REQ_MASK (BIT(1) | BIT(0)) 115*4882a593Smuzhiyun #define CRYP_DMA_REQ_MASK_POS 0 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct cryp_system_context { 119*4882a593Smuzhiyun /* CRYP Register structure */ 120*4882a593Smuzhiyun struct cryp_register *p_cryp_reg[MAX_DEVICE_SUPPORT]; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124