xref: /OK3568_Linux_fs/kernel/drivers/crypto/ux500/cryp/cryp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson SA 2010
4*4882a593Smuzhiyun  * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
5*4882a593Smuzhiyun  * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
6*4882a593Smuzhiyun  * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
7*4882a593Smuzhiyun  * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
8*4882a593Smuzhiyun  * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef _CRYP_H_
12*4882a593Smuzhiyun #define _CRYP_H_
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/completion.h>
15*4882a593Smuzhiyun #include <linux/dmaengine.h>
16*4882a593Smuzhiyun #include <linux/klist.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define DEV_DBG_NAME "crypX crypX:"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* CRYP enable/disable */
22*4882a593Smuzhiyun enum cryp_crypen {
23*4882a593Smuzhiyun 	CRYP_CRYPEN_DISABLE = 0,
24*4882a593Smuzhiyun 	CRYP_CRYPEN_ENABLE = 1
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* CRYP Start Computation enable/disable */
28*4882a593Smuzhiyun enum cryp_start {
29*4882a593Smuzhiyun 	CRYP_START_DISABLE = 0,
30*4882a593Smuzhiyun 	CRYP_START_ENABLE = 1
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* CRYP Init Signal enable/disable */
34*4882a593Smuzhiyun enum cryp_init {
35*4882a593Smuzhiyun 	CRYP_INIT_DISABLE = 0,
36*4882a593Smuzhiyun 	CRYP_INIT_ENABLE = 1
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* Cryp State enable/disable */
40*4882a593Smuzhiyun enum cryp_state {
41*4882a593Smuzhiyun 	CRYP_STATE_DISABLE = 0,
42*4882a593Smuzhiyun 	CRYP_STATE_ENABLE = 1
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* Key preparation bit enable */
46*4882a593Smuzhiyun enum cryp_key_prep {
47*4882a593Smuzhiyun 	KSE_DISABLED = 0,
48*4882a593Smuzhiyun 	KSE_ENABLED = 1
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* Key size for AES */
52*4882a593Smuzhiyun #define	CRYP_KEY_SIZE_128 (0)
53*4882a593Smuzhiyun #define	CRYP_KEY_SIZE_192 (1)
54*4882a593Smuzhiyun #define	CRYP_KEY_SIZE_256 (2)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* AES modes */
57*4882a593Smuzhiyun enum cryp_algo_mode {
58*4882a593Smuzhiyun 	CRYP_ALGO_TDES_ECB,
59*4882a593Smuzhiyun 	CRYP_ALGO_TDES_CBC,
60*4882a593Smuzhiyun 	CRYP_ALGO_DES_ECB,
61*4882a593Smuzhiyun 	CRYP_ALGO_DES_CBC,
62*4882a593Smuzhiyun 	CRYP_ALGO_AES_ECB,
63*4882a593Smuzhiyun 	CRYP_ALGO_AES_CBC,
64*4882a593Smuzhiyun 	CRYP_ALGO_AES_CTR,
65*4882a593Smuzhiyun 	CRYP_ALGO_AES_XTS
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* Cryp Encryption or Decryption */
69*4882a593Smuzhiyun enum cryp_algorithm_dir {
70*4882a593Smuzhiyun 	CRYP_ALGORITHM_ENCRYPT,
71*4882a593Smuzhiyun 	CRYP_ALGORITHM_DECRYPT
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /* Hardware access method */
75*4882a593Smuzhiyun enum cryp_mode {
76*4882a593Smuzhiyun 	CRYP_MODE_POLLING,
77*4882a593Smuzhiyun 	CRYP_MODE_INTERRUPT,
78*4882a593Smuzhiyun 	CRYP_MODE_DMA
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /**
82*4882a593Smuzhiyun  * struct cryp_config -
83*4882a593Smuzhiyun  * @keysize: Key size for AES
84*4882a593Smuzhiyun  * @algomode: AES modes
85*4882a593Smuzhiyun  * @algodir: Cryp Encryption or Decryption
86*4882a593Smuzhiyun  *
87*4882a593Smuzhiyun  * CRYP configuration structure to be passed to set configuration
88*4882a593Smuzhiyun  */
89*4882a593Smuzhiyun struct cryp_config {
90*4882a593Smuzhiyun 	int keysize;
91*4882a593Smuzhiyun 	enum cryp_algo_mode algomode;
92*4882a593Smuzhiyun 	enum cryp_algorithm_dir algodir;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /**
96*4882a593Smuzhiyun  * struct cryp_protection_config -
97*4882a593Smuzhiyun  * @privilege_access: Privileged cryp state enable/disable
98*4882a593Smuzhiyun  * @secure_access: Secure cryp state enable/disable
99*4882a593Smuzhiyun  *
100*4882a593Smuzhiyun  * Protection configuration structure for setting privilage access
101*4882a593Smuzhiyun  */
102*4882a593Smuzhiyun struct cryp_protection_config {
103*4882a593Smuzhiyun 	enum cryp_state privilege_access;
104*4882a593Smuzhiyun 	enum cryp_state secure_access;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Cryp status */
108*4882a593Smuzhiyun enum cryp_status_id {
109*4882a593Smuzhiyun 	CRYP_STATUS_BUSY = 0x10,
110*4882a593Smuzhiyun 	CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
111*4882a593Smuzhiyun 	CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
112*4882a593Smuzhiyun 	CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
113*4882a593Smuzhiyun 	CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun /* Cryp DMA interface */
117*4882a593Smuzhiyun #define CRYP_DMA_TX_FIFO	0x08
118*4882a593Smuzhiyun #define CRYP_DMA_RX_FIFO	0x10
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun enum cryp_dma_req_type {
121*4882a593Smuzhiyun 	CRYP_DMA_DISABLE_BOTH,
122*4882a593Smuzhiyun 	CRYP_DMA_ENABLE_IN_DATA,
123*4882a593Smuzhiyun 	CRYP_DMA_ENABLE_OUT_DATA,
124*4882a593Smuzhiyun 	CRYP_DMA_ENABLE_BOTH_DIRECTIONS
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun enum cryp_dma_channel {
128*4882a593Smuzhiyun 	CRYP_DMA_RX = 0,
129*4882a593Smuzhiyun 	CRYP_DMA_TX
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* Key registers */
133*4882a593Smuzhiyun enum cryp_key_reg_index {
134*4882a593Smuzhiyun 	CRYP_KEY_REG_1,
135*4882a593Smuzhiyun 	CRYP_KEY_REG_2,
136*4882a593Smuzhiyun 	CRYP_KEY_REG_3,
137*4882a593Smuzhiyun 	CRYP_KEY_REG_4
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* Key register left and right */
141*4882a593Smuzhiyun struct cryp_key_value {
142*4882a593Smuzhiyun 	u32 key_value_left;
143*4882a593Smuzhiyun 	u32 key_value_right;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* Cryp Initialization structure */
147*4882a593Smuzhiyun enum cryp_init_vector_index {
148*4882a593Smuzhiyun 	CRYP_INIT_VECTOR_INDEX_0,
149*4882a593Smuzhiyun 	CRYP_INIT_VECTOR_INDEX_1
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* struct cryp_init_vector_value -
153*4882a593Smuzhiyun  * @init_value_left
154*4882a593Smuzhiyun  * @init_value_right
155*4882a593Smuzhiyun  * */
156*4882a593Smuzhiyun struct cryp_init_vector_value {
157*4882a593Smuzhiyun 	u32 init_value_left;
158*4882a593Smuzhiyun 	u32 init_value_right;
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /**
162*4882a593Smuzhiyun  * struct cryp_device_context - structure for a cryp context.
163*4882a593Smuzhiyun  * @cr: control register
164*4882a593Smuzhiyun  * @dmacr: DMA control register
165*4882a593Smuzhiyun  * @imsc: Interrupt mask set/clear register
166*4882a593Smuzhiyun  * @key_1_l: Key 1l register
167*4882a593Smuzhiyun  * @key_1_r: Key 1r register
168*4882a593Smuzhiyun  * @key_2_l: Key 2l register
169*4882a593Smuzhiyun  * @key_2_r: Key 2r register
170*4882a593Smuzhiyun  * @key_3_l: Key 3l register
171*4882a593Smuzhiyun  * @key_3_r: Key 3r register
172*4882a593Smuzhiyun  * @key_4_l: Key 4l register
173*4882a593Smuzhiyun  * @key_4_r: Key 4r register
174*4882a593Smuzhiyun  * @init_vect_0_l: Initialization vector 0l register
175*4882a593Smuzhiyun  * @init_vect_0_r: Initialization vector 0r register
176*4882a593Smuzhiyun  * @init_vect_1_l: Initialization vector 1l register
177*4882a593Smuzhiyun  * @init_vect_1_r: Initialization vector 0r register
178*4882a593Smuzhiyun  * @din: Data in register
179*4882a593Smuzhiyun  * @dout: Data out register
180*4882a593Smuzhiyun  *
181*4882a593Smuzhiyun  * CRYP power management specifc structure.
182*4882a593Smuzhiyun  */
183*4882a593Smuzhiyun struct cryp_device_context {
184*4882a593Smuzhiyun 	u32 cr;
185*4882a593Smuzhiyun 	u32 dmacr;
186*4882a593Smuzhiyun 	u32 imsc;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	u32 key_1_l;
189*4882a593Smuzhiyun 	u32 key_1_r;
190*4882a593Smuzhiyun 	u32 key_2_l;
191*4882a593Smuzhiyun 	u32 key_2_r;
192*4882a593Smuzhiyun 	u32 key_3_l;
193*4882a593Smuzhiyun 	u32 key_3_r;
194*4882a593Smuzhiyun 	u32 key_4_l;
195*4882a593Smuzhiyun 	u32 key_4_r;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	u32 init_vect_0_l;
198*4882a593Smuzhiyun 	u32 init_vect_0_r;
199*4882a593Smuzhiyun 	u32 init_vect_1_l;
200*4882a593Smuzhiyun 	u32 init_vect_1_r;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	u32 din;
203*4882a593Smuzhiyun 	u32 dout;
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun struct cryp_dma {
207*4882a593Smuzhiyun 	dma_cap_mask_t mask;
208*4882a593Smuzhiyun 	struct completion cryp_dma_complete;
209*4882a593Smuzhiyun 	struct dma_chan *chan_cryp2mem;
210*4882a593Smuzhiyun 	struct dma_chan *chan_mem2cryp;
211*4882a593Smuzhiyun 	struct stedma40_chan_cfg *cfg_cryp2mem;
212*4882a593Smuzhiyun 	struct stedma40_chan_cfg *cfg_mem2cryp;
213*4882a593Smuzhiyun 	int sg_src_len;
214*4882a593Smuzhiyun 	int sg_dst_len;
215*4882a593Smuzhiyun 	struct scatterlist *sg_src;
216*4882a593Smuzhiyun 	struct scatterlist *sg_dst;
217*4882a593Smuzhiyun 	int nents_src;
218*4882a593Smuzhiyun 	int nents_dst;
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun /**
222*4882a593Smuzhiyun  * struct cryp_device_data - structure for a cryp device.
223*4882a593Smuzhiyun  * @base: Pointer to virtual base address of the cryp device.
224*4882a593Smuzhiyun  * @phybase: Pointer to physical memory location of the cryp device.
225*4882a593Smuzhiyun  * @dev: Pointer to the devices dev structure.
226*4882a593Smuzhiyun  * @clk: Pointer to the device's clock control.
227*4882a593Smuzhiyun  * @pwr_regulator: Pointer to the device's power control.
228*4882a593Smuzhiyun  * @power_status: Current status of the power.
229*4882a593Smuzhiyun  * @ctx_lock: Lock for current_ctx.
230*4882a593Smuzhiyun  * @current_ctx: Pointer to the currently allocated context.
231*4882a593Smuzhiyun  * @list_node: For inclusion into a klist.
232*4882a593Smuzhiyun  * @dma: The dma structure holding channel configuration.
233*4882a593Smuzhiyun  * @power_state: TRUE = power state on, FALSE = power state off.
234*4882a593Smuzhiyun  * @power_state_spinlock: Spinlock for power_state.
235*4882a593Smuzhiyun  * @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
236*4882a593Smuzhiyun  */
237*4882a593Smuzhiyun struct cryp_device_data {
238*4882a593Smuzhiyun 	struct cryp_register __iomem *base;
239*4882a593Smuzhiyun 	phys_addr_t phybase;
240*4882a593Smuzhiyun 	struct device *dev;
241*4882a593Smuzhiyun 	struct clk *clk;
242*4882a593Smuzhiyun 	struct regulator *pwr_regulator;
243*4882a593Smuzhiyun 	int power_status;
244*4882a593Smuzhiyun 	spinlock_t ctx_lock;
245*4882a593Smuzhiyun 	struct cryp_ctx *current_ctx;
246*4882a593Smuzhiyun 	struct klist_node list_node;
247*4882a593Smuzhiyun 	struct cryp_dma dma;
248*4882a593Smuzhiyun 	bool power_state;
249*4882a593Smuzhiyun 	spinlock_t power_state_spinlock;
250*4882a593Smuzhiyun 	bool restore_dev_ctx;
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun void cryp_wait_until_done(struct cryp_device_data *device_data);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun /* Initialization functions */
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun int cryp_check(struct cryp_device_data *device_data);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun void cryp_activity(struct cryp_device_data *device_data,
260*4882a593Smuzhiyun 		   enum cryp_crypen cryp_crypen);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun void cryp_flush_inoutfifo(struct cryp_device_data *device_data);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun int cryp_set_configuration(struct cryp_device_data *device_data,
265*4882a593Smuzhiyun 			   struct cryp_config *cryp_config,
266*4882a593Smuzhiyun 			   u32 *control_register);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun void cryp_configure_for_dma(struct cryp_device_data *device_data,
269*4882a593Smuzhiyun 			    enum cryp_dma_req_type dma_req);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun int cryp_configure_key_values(struct cryp_device_data *device_data,
272*4882a593Smuzhiyun 			      enum cryp_key_reg_index key_reg_index,
273*4882a593Smuzhiyun 			      struct cryp_key_value key_value);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun int cryp_configure_init_vector(struct cryp_device_data *device_data,
276*4882a593Smuzhiyun 			       enum cryp_init_vector_index
277*4882a593Smuzhiyun 			       init_vector_index,
278*4882a593Smuzhiyun 			       struct cryp_init_vector_value
279*4882a593Smuzhiyun 			       init_vector_value);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun int cryp_configure_protection(struct cryp_device_data *device_data,
282*4882a593Smuzhiyun 			      struct cryp_protection_config *p_protect_config);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun /* Power management funtions */
285*4882a593Smuzhiyun void cryp_save_device_context(struct cryp_device_data *device_data,
286*4882a593Smuzhiyun 			      struct cryp_device_context *ctx,
287*4882a593Smuzhiyun 			      int cryp_mode);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun void cryp_restore_device_context(struct cryp_device_data *device_data,
290*4882a593Smuzhiyun 				 struct cryp_device_context *ctx);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun /* Data transfer and status bits. */
293*4882a593Smuzhiyun int cryp_is_logic_busy(struct cryp_device_data *device_data);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun int cryp_get_status(struct cryp_device_data *device_data);
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /**
298*4882a593Smuzhiyun  * cryp_write_indata - This routine writes 32 bit data into the data input
299*4882a593Smuzhiyun  *		       register of the cryptography IP.
300*4882a593Smuzhiyun  * @device_data: Pointer to the device data struct for base address.
301*4882a593Smuzhiyun  * @write_data: Data to write.
302*4882a593Smuzhiyun  */
303*4882a593Smuzhiyun int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun /**
306*4882a593Smuzhiyun  * cryp_read_outdata - This routine reads the data from the data output
307*4882a593Smuzhiyun  *		       register of the CRYP logic
308*4882a593Smuzhiyun  * @device_data: Pointer to the device data struct for base address.
309*4882a593Smuzhiyun  * @read_data: Read the data from the output FIFO.
310*4882a593Smuzhiyun  */
311*4882a593Smuzhiyun int cryp_read_outdata(struct cryp_device_data *device_data, u32 *read_data);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun #endif /* _CRYP_H_ */
314