1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Crypto acceleration support for Rockchip Crypto V2
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2022, Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Lin Jinhan <troy.lin@rock-chips.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "rk_crypto_core.h"
12*4882a593Smuzhiyun #include "rk_crypto_v2.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static const char * const crypto_v2_rsts[] = {
15*4882a593Smuzhiyun "crypto-rst",
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static struct rk_crypto_algt *crypto_v2_algs[] = {
19*4882a593Smuzhiyun &rk_v2_ecb_sm4_alg, /* ecb(sm4) */
20*4882a593Smuzhiyun &rk_v2_cbc_sm4_alg, /* cbc(sm4) */
21*4882a593Smuzhiyun &rk_v2_xts_sm4_alg, /* xts(sm4) */
22*4882a593Smuzhiyun &rk_v2_cfb_sm4_alg, /* cfb(sm4) */
23*4882a593Smuzhiyun &rk_v2_ofb_sm4_alg, /* ofb(sm4) */
24*4882a593Smuzhiyun &rk_v2_ctr_sm4_alg, /* ctr(sm4) */
25*4882a593Smuzhiyun &rk_v2_gcm_sm4_alg, /* gcm(sm4) */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun &rk_v2_ecb_aes_alg, /* ecb(aes) */
28*4882a593Smuzhiyun &rk_v2_cbc_aes_alg, /* cbc(aes) */
29*4882a593Smuzhiyun &rk_v2_xts_aes_alg, /* xts(aes) */
30*4882a593Smuzhiyun &rk_v2_cfb_aes_alg, /* cfb(aes) */
31*4882a593Smuzhiyun &rk_v2_ofb_aes_alg, /* ofb(aes) */
32*4882a593Smuzhiyun &rk_v2_ctr_aes_alg, /* ctr(aes) */
33*4882a593Smuzhiyun &rk_v2_gcm_aes_alg, /* gcm(aes) */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun &rk_v2_ecb_des_alg, /* ecb(des) */
36*4882a593Smuzhiyun &rk_v2_cbc_des_alg, /* cbc(des) */
37*4882a593Smuzhiyun &rk_v2_cfb_des_alg, /* cfb(des) */
38*4882a593Smuzhiyun &rk_v2_ofb_des_alg, /* ofb(des) */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun &rk_v2_ecb_des3_ede_alg, /* ecb(des3_ede) */
41*4882a593Smuzhiyun &rk_v2_cbc_des3_ede_alg, /* cbc(des3_ede) */
42*4882a593Smuzhiyun &rk_v2_cfb_des3_ede_alg, /* cfb(des3_ede) */
43*4882a593Smuzhiyun &rk_v2_ofb_des3_ede_alg, /* ofb(des3_ede) */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun &rk_v2_ahash_sha1, /* sha1 */
46*4882a593Smuzhiyun &rk_v2_ahash_sha224, /* sha224 */
47*4882a593Smuzhiyun &rk_v2_ahash_sha256, /* sha256 */
48*4882a593Smuzhiyun &rk_v2_ahash_sha384, /* sha384 */
49*4882a593Smuzhiyun &rk_v2_ahash_sha512, /* sha512 */
50*4882a593Smuzhiyun &rk_v2_ahash_md5, /* md5 */
51*4882a593Smuzhiyun &rk_v2_ahash_sm3, /* sm3 */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun &rk_v2_hmac_sha1, /* hmac(sha1) */
54*4882a593Smuzhiyun &rk_v2_hmac_sha256, /* hmac(sha256) */
55*4882a593Smuzhiyun &rk_v2_hmac_sha512, /* hmac(sha512) */
56*4882a593Smuzhiyun &rk_v2_hmac_md5, /* hmac(md5) */
57*4882a593Smuzhiyun &rk_v2_hmac_sm3, /* hmac(sm3) */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun &rk_v2_asym_rsa, /* rsa */
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
rk_hw_crypto_v2_init(struct device * dev,void * hw_info)62*4882a593Smuzhiyun int rk_hw_crypto_v2_init(struct device *dev, void *hw_info)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct rk_hw_crypto_v2_info *info =
65*4882a593Smuzhiyun (struct rk_hw_crypto_v2_info *)hw_info;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (!dev || !hw_info)
68*4882a593Smuzhiyun return -EINVAL;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun memset(info, 0x00, sizeof(*info));
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return rk_crypto_hw_desc_alloc(dev, &info->hw_desc);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
rk_hw_crypto_v2_deinit(struct device * dev,void * hw_info)75*4882a593Smuzhiyun void rk_hw_crypto_v2_deinit(struct device *dev, void *hw_info)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct rk_hw_crypto_v2_info *info =
78*4882a593Smuzhiyun (struct rk_hw_crypto_v2_info *)hw_info;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (!dev || !hw_info)
81*4882a593Smuzhiyun return;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun rk_crypto_hw_desc_free(&info->hw_desc);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
rk_hw_crypto_v2_get_rsts(uint32_t * num)86*4882a593Smuzhiyun const char * const *rk_hw_crypto_v2_get_rsts(uint32_t *num)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun *num = ARRAY_SIZE(crypto_v2_rsts);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return crypto_v2_rsts;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
rk_hw_crypto_v2_get_algts(uint32_t * num)93*4882a593Smuzhiyun struct rk_crypto_algt **rk_hw_crypto_v2_get_algts(uint32_t *num)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun *num = ARRAY_SIZE(crypto_v2_algs);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return crypto_v2_algs;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
rk_hw_crypto_v2_algo_valid(struct rk_crypto_dev * rk_dev,struct rk_crypto_algt * aglt)100*4882a593Smuzhiyun bool rk_hw_crypto_v2_algo_valid(struct rk_crypto_dev *rk_dev, struct rk_crypto_algt *aglt)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun return true;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105