1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifndef __RK_CRYPTO_V1_H__
6*4882a593Smuzhiyun #define __RK_CRYPTO_V1_H__
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun struct rk_hw_crypto_v1_info {
11*4882a593Smuzhiyun int reserved;
12*4882a593Smuzhiyun };
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define RK_CRYPTO_V1_SOC_DATA_INIT(names) {\
15*4882a593Smuzhiyun .crypto_ver = "CRYPTO V1.0.0.0",\
16*4882a593Smuzhiyun .use_soft_aes192 = false,\
17*4882a593Smuzhiyun .valid_algs_name = (names),\
18*4882a593Smuzhiyun .valid_algs_num = ARRAY_SIZE(names),\
19*4882a593Smuzhiyun .hw_init = rk_hw_crypto_v1_init,\
20*4882a593Smuzhiyun .hw_deinit = rk_hw_crypto_v1_deinit,\
21*4882a593Smuzhiyun .hw_get_rsts = rk_hw_crypto_v1_get_rsts,\
22*4882a593Smuzhiyun .hw_get_algts = rk_hw_crypto_v1_get_algts,\
23*4882a593Smuzhiyun .hw_is_algo_valid = rk_hw_crypto_v1_algo_valid,\
24*4882a593Smuzhiyun .hw_info_size = sizeof(struct rk_hw_crypto_v1_info),\
25*4882a593Smuzhiyun .default_pka_offset = 0,\
26*4882a593Smuzhiyun .use_lli_chain = false,\
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CRYPTO_DEV_ROCKCHIP_V1)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ecb_aes_alg;
32*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_cbc_aes_alg;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ecb_des_alg;
35*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_cbc_des_alg;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ecb_des3_ede_alg;
38*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_cbc_des3_ede_alg;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ahash_sha1;
41*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ahash_sha256;
42*4882a593Smuzhiyun extern struct rk_crypto_algt rk_v1_ahash_md5;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun int rk_hw_crypto_v1_init(struct device *dev, void *hw_info);
45*4882a593Smuzhiyun void rk_hw_crypto_v1_deinit(struct device *dev, void *hw_info);
46*4882a593Smuzhiyun const char * const *rk_hw_crypto_v1_get_rsts(uint32_t *num);
47*4882a593Smuzhiyun struct rk_crypto_algt **rk_hw_crypto_v1_get_algts(uint32_t *num);
48*4882a593Smuzhiyun bool rk_hw_crypto_v1_algo_valid(struct rk_crypto_dev *rk_dev, struct rk_crypto_algt *aglt);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #else
51*4882a593Smuzhiyun
rk_hw_crypto_v1_init(struct device * dev,void * hw_info)52*4882a593Smuzhiyun static inline int rk_hw_crypto_v1_init(struct device *dev, void *hw_info) { return -EINVAL; }
rk_hw_crypto_v1_deinit(struct device * dev,void * hw_info)53*4882a593Smuzhiyun static inline void rk_hw_crypto_v1_deinit(struct device *dev, void *hw_info) {}
rk_hw_crypto_v1_get_rsts(uint32_t * num)54*4882a593Smuzhiyun static inline const char * const *rk_hw_crypto_v1_get_rsts(uint32_t *num) { return NULL; }
rk_hw_crypto_v1_get_algts(uint32_t * num)55*4882a593Smuzhiyun static inline struct rk_crypto_algt **rk_hw_crypto_v1_get_algts(uint32_t *num) { return NULL; }
rk_hw_crypto_v1_algo_valid(struct rk_crypto_dev * rk_dev,struct rk_crypto_algt * aglt)56*4882a593Smuzhiyun static inline bool rk_hw_crypto_v1_algo_valid(struct rk_crypto_dev *rk_dev,
57*4882a593Smuzhiyun struct rk_crypto_algt *aglt)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return false;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #endif /* end of IS_ENABLED(CONFIG_CRYPTO_DEV_ROCKCHIP_V1) */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #endif /* end of __RK_CRYPTO_V1_H__ */
65*4882a593Smuzhiyun
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