1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Crypto acceleration support for Rockchip Crypto V1
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2022, Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Lin Jinhan <troy.lin@rock-chips.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include "rk_crypto_core.h"
11*4882a593Smuzhiyun #include "rk_crypto_v1.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static const char * const crypto_v1_rsts[] = {
14*4882a593Smuzhiyun "crypto-rst",
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static struct rk_crypto_algt *crypto_v1_algs[] = {
18*4882a593Smuzhiyun &rk_v1_ecb_aes_alg, /* ecb(aes) */
19*4882a593Smuzhiyun &rk_v1_cbc_aes_alg, /* cbc(aes) */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun &rk_v1_ecb_des_alg, /* ecb(des) */
22*4882a593Smuzhiyun &rk_v1_cbc_des_alg, /* cbc(des) */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun &rk_v1_ecb_des3_ede_alg, /* ecb(des3_ede) */
25*4882a593Smuzhiyun &rk_v1_cbc_des3_ede_alg, /* cbc(des3_ede) */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun &rk_v1_ahash_sha1, /* sha1 */
28*4882a593Smuzhiyun &rk_v1_ahash_sha256, /* sha256 */
29*4882a593Smuzhiyun &rk_v1_ahash_md5, /* md5 */
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
rk_hw_crypto_v1_init(struct device * dev,void * hw_info)32*4882a593Smuzhiyun int rk_hw_crypto_v1_init(struct device *dev, void *hw_info)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
rk_hw_crypto_v1_deinit(struct device * dev,void * hw_info)37*4882a593Smuzhiyun void rk_hw_crypto_v1_deinit(struct device *dev, void *hw_info)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
rk_hw_crypto_v1_get_rsts(uint32_t * num)42*4882a593Smuzhiyun const char * const *rk_hw_crypto_v1_get_rsts(uint32_t *num)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun *num = ARRAY_SIZE(crypto_v1_rsts);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return crypto_v1_rsts;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
rk_hw_crypto_v1_get_algts(uint32_t * num)49*4882a593Smuzhiyun struct rk_crypto_algt **rk_hw_crypto_v1_get_algts(uint32_t *num)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun *num = ARRAY_SIZE(crypto_v1_algs);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return crypto_v1_algs;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
rk_hw_crypto_v1_algo_valid(struct rk_crypto_dev * rk_dev,struct rk_crypto_algt * aglt)56*4882a593Smuzhiyun bool rk_hw_crypto_v1_algo_valid(struct rk_crypto_dev *rk_dev, struct rk_crypto_algt *aglt)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun return true;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61