xref: /OK3568_Linux_fs/kernel/drivers/crypto/qce/dma.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _DMA_H_
7*4882a593Smuzhiyun #define _DMA_H_
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/dmaengine.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* maximum data transfer block size between BAM and CE */
12*4882a593Smuzhiyun #define QCE_BAM_BURST_SIZE		64
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define QCE_AUTHIV_REGS_CNT		16
15*4882a593Smuzhiyun #define QCE_AUTH_BYTECOUNT_REGS_CNT	4
16*4882a593Smuzhiyun #define QCE_CNTRIV_REGS_CNT		4
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun struct qce_result_dump {
19*4882a593Smuzhiyun 	u32 auth_iv[QCE_AUTHIV_REGS_CNT];
20*4882a593Smuzhiyun 	u32 auth_byte_count[QCE_AUTH_BYTECOUNT_REGS_CNT];
21*4882a593Smuzhiyun 	u32 encr_cntr_iv[QCE_CNTRIV_REGS_CNT];
22*4882a593Smuzhiyun 	u32 status;
23*4882a593Smuzhiyun 	u32 status2;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define QCE_IGNORE_BUF_SZ	(2 * QCE_BAM_BURST_SIZE)
27*4882a593Smuzhiyun #define QCE_RESULT_BUF_SZ	\
28*4882a593Smuzhiyun 		ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct qce_dma_data {
31*4882a593Smuzhiyun 	struct dma_chan *txchan;
32*4882a593Smuzhiyun 	struct dma_chan *rxchan;
33*4882a593Smuzhiyun 	struct qce_result_dump *result_buf;
34*4882a593Smuzhiyun 	void *ignore_buf;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun int qce_dma_request(struct device *dev, struct qce_dma_data *dma);
38*4882a593Smuzhiyun void qce_dma_release(struct qce_dma_data *dma);
39*4882a593Smuzhiyun int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in,
40*4882a593Smuzhiyun 		     int in_ents, struct scatterlist *sg_out, int out_ents,
41*4882a593Smuzhiyun 		     dma_async_tx_callback cb, void *cb_param);
42*4882a593Smuzhiyun void qce_dma_issue_pending(struct qce_dma_data *dma);
43*4882a593Smuzhiyun int qce_dma_terminate_all(struct qce_dma_data *dma);
44*4882a593Smuzhiyun struct scatterlist *
45*4882a593Smuzhiyun qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
46*4882a593Smuzhiyun 		unsigned int max_len);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #endif /* _DMA_H_ */
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