xref: /OK3568_Linux_fs/kernel/drivers/crypto/qat/qat_common/adf_isr.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2*4882a593Smuzhiyun /* Copyright(c) 2014 - 2020 Intel Corporation */
3*4882a593Smuzhiyun #include <linux/kernel.h>
4*4882a593Smuzhiyun #include <linux/init.h>
5*4882a593Smuzhiyun #include <linux/types.h>
6*4882a593Smuzhiyun #include <linux/pci.h>
7*4882a593Smuzhiyun #include <linux/slab.h>
8*4882a593Smuzhiyun #include <linux/errno.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include "adf_accel_devices.h"
11*4882a593Smuzhiyun #include "adf_common_drv.h"
12*4882a593Smuzhiyun #include "adf_cfg.h"
13*4882a593Smuzhiyun #include "adf_cfg_strings.h"
14*4882a593Smuzhiyun #include "adf_cfg_common.h"
15*4882a593Smuzhiyun #include "adf_transport_access_macros.h"
16*4882a593Smuzhiyun #include "adf_transport_internal.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define ADF_MAX_NUM_VFS	32
19*4882a593Smuzhiyun 
adf_enable_msix(struct adf_accel_dev * accel_dev)20*4882a593Smuzhiyun static int adf_enable_msix(struct adf_accel_dev *accel_dev)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun 	struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
23*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
24*4882a593Smuzhiyun 	u32 msix_num_entries = 1;
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	/* If SR-IOV is disabled, add entries for each bank */
27*4882a593Smuzhiyun 	if (!accel_dev->pf.vf_info) {
28*4882a593Smuzhiyun 		int i;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 		msix_num_entries += hw_data->num_banks;
31*4882a593Smuzhiyun 		for (i = 0; i < msix_num_entries; i++)
32*4882a593Smuzhiyun 			pci_dev_info->msix_entries.entries[i].entry = i;
33*4882a593Smuzhiyun 	} else {
34*4882a593Smuzhiyun 		pci_dev_info->msix_entries.entries[0].entry =
35*4882a593Smuzhiyun 			hw_data->num_banks;
36*4882a593Smuzhiyun 	}
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	if (pci_enable_msix_exact(pci_dev_info->pci_dev,
39*4882a593Smuzhiyun 				  pci_dev_info->msix_entries.entries,
40*4882a593Smuzhiyun 				  msix_num_entries)) {
41*4882a593Smuzhiyun 		dev_err(&GET_DEV(accel_dev), "Failed to enable MSI-X IRQ(s)\n");
42*4882a593Smuzhiyun 		return -EFAULT;
43*4882a593Smuzhiyun 	}
44*4882a593Smuzhiyun 	return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun 
adf_disable_msix(struct adf_accel_pci * pci_dev_info)47*4882a593Smuzhiyun static void adf_disable_msix(struct adf_accel_pci *pci_dev_info)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	pci_disable_msix(pci_dev_info->pci_dev);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun 
adf_msix_isr_bundle(int irq,void * bank_ptr)52*4882a593Smuzhiyun static irqreturn_t adf_msix_isr_bundle(int irq, void *bank_ptr)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	struct adf_etr_bank_data *bank = bank_ptr;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0);
57*4882a593Smuzhiyun 	tasklet_hi_schedule(&bank->resp_handler);
58*4882a593Smuzhiyun 	return IRQ_HANDLED;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
adf_msix_isr_ae(int irq,void * dev_ptr)61*4882a593Smuzhiyun static irqreturn_t adf_msix_isr_ae(int irq, void *dev_ptr)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct adf_accel_dev *accel_dev = dev_ptr;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #ifdef CONFIG_PCI_IOV
66*4882a593Smuzhiyun 	/* If SR-IOV is enabled (vf_info is non-NULL), check for VF->PF ints */
67*4882a593Smuzhiyun 	if (accel_dev->pf.vf_info) {
68*4882a593Smuzhiyun 		struct adf_hw_device_data *hw_data = accel_dev->hw_device;
69*4882a593Smuzhiyun 		struct adf_bar *pmisc =
70*4882a593Smuzhiyun 			&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
71*4882a593Smuzhiyun 		void __iomem *pmisc_bar_addr = pmisc->virt_addr;
72*4882a593Smuzhiyun 		unsigned long vf_mask;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 		/* Get the interrupt sources triggered by VFs */
75*4882a593Smuzhiyun 		vf_mask = ((ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU5) &
76*4882a593Smuzhiyun 			    0x0000FFFF) << 16) |
77*4882a593Smuzhiyun 			  ((ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU3) &
78*4882a593Smuzhiyun 			    0x01FFFE00) >> 9);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 		if (vf_mask) {
81*4882a593Smuzhiyun 			struct adf_accel_vf_info *vf_info;
82*4882a593Smuzhiyun 			bool irq_handled = false;
83*4882a593Smuzhiyun 			int i;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 			/* Disable VF2PF interrupts for VFs with pending ints */
86*4882a593Smuzhiyun 			adf_disable_vf2pf_interrupts(accel_dev, vf_mask);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 			/*
89*4882a593Smuzhiyun 			 * Schedule tasklets to handle VF2PF interrupt BHs
90*4882a593Smuzhiyun 			 * unless the VF is malicious and is attempting to
91*4882a593Smuzhiyun 			 * flood the host OS with VF2PF interrupts.
92*4882a593Smuzhiyun 			 */
93*4882a593Smuzhiyun 			for_each_set_bit(i, &vf_mask, ADF_MAX_NUM_VFS) {
94*4882a593Smuzhiyun 				vf_info = accel_dev->pf.vf_info + i;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 				if (!__ratelimit(&vf_info->vf2pf_ratelimit)) {
97*4882a593Smuzhiyun 					dev_info(&GET_DEV(accel_dev),
98*4882a593Smuzhiyun 						 "Too many ints from VF%d\n",
99*4882a593Smuzhiyun 						  vf_info->vf_nr + 1);
100*4882a593Smuzhiyun 					continue;
101*4882a593Smuzhiyun 				}
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 				/* Tasklet will re-enable ints from this VF */
104*4882a593Smuzhiyun 				tasklet_hi_schedule(&vf_info->vf2pf_bh_tasklet);
105*4882a593Smuzhiyun 				irq_handled = true;
106*4882a593Smuzhiyun 			}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 			if (irq_handled)
109*4882a593Smuzhiyun 				return IRQ_HANDLED;
110*4882a593Smuzhiyun 		}
111*4882a593Smuzhiyun 	}
112*4882a593Smuzhiyun #endif /* CONFIG_PCI_IOV */
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	dev_dbg(&GET_DEV(accel_dev), "qat_dev%d spurious AE interrupt\n",
115*4882a593Smuzhiyun 		accel_dev->accel_id);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return IRQ_NONE;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
adf_request_irqs(struct adf_accel_dev * accel_dev)120*4882a593Smuzhiyun static int adf_request_irqs(struct adf_accel_dev *accel_dev)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
123*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
124*4882a593Smuzhiyun 	struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
125*4882a593Smuzhiyun 	struct adf_etr_data *etr_data = accel_dev->transport;
126*4882a593Smuzhiyun 	int ret, i = 0;
127*4882a593Smuzhiyun 	char *name;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* Request msix irq for all banks unless SR-IOV enabled */
130*4882a593Smuzhiyun 	if (!accel_dev->pf.vf_info) {
131*4882a593Smuzhiyun 		for (i = 0; i < hw_data->num_banks; i++) {
132*4882a593Smuzhiyun 			struct adf_etr_bank_data *bank = &etr_data->banks[i];
133*4882a593Smuzhiyun 			unsigned int cpu, cpus = num_online_cpus();
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 			name = *(pci_dev_info->msix_entries.names + i);
136*4882a593Smuzhiyun 			snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
137*4882a593Smuzhiyun 				 "qat%d-bundle%d", accel_dev->accel_id, i);
138*4882a593Smuzhiyun 			ret = request_irq(msixe[i].vector,
139*4882a593Smuzhiyun 					  adf_msix_isr_bundle, 0, name, bank);
140*4882a593Smuzhiyun 			if (ret) {
141*4882a593Smuzhiyun 				dev_err(&GET_DEV(accel_dev),
142*4882a593Smuzhiyun 					"failed to enable irq %d for %s\n",
143*4882a593Smuzhiyun 					msixe[i].vector, name);
144*4882a593Smuzhiyun 				return ret;
145*4882a593Smuzhiyun 			}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 			cpu = ((accel_dev->accel_id * hw_data->num_banks) +
148*4882a593Smuzhiyun 			       i) % cpus;
149*4882a593Smuzhiyun 			irq_set_affinity_hint(msixe[i].vector,
150*4882a593Smuzhiyun 					      get_cpu_mask(cpu));
151*4882a593Smuzhiyun 		}
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* Request msix irq for AE */
155*4882a593Smuzhiyun 	name = *(pci_dev_info->msix_entries.names + i);
156*4882a593Smuzhiyun 	snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
157*4882a593Smuzhiyun 		 "qat%d-ae-cluster", accel_dev->accel_id);
158*4882a593Smuzhiyun 	ret = request_irq(msixe[i].vector, adf_msix_isr_ae, 0, name, accel_dev);
159*4882a593Smuzhiyun 	if (ret) {
160*4882a593Smuzhiyun 		dev_err(&GET_DEV(accel_dev),
161*4882a593Smuzhiyun 			"failed to enable irq %d, for %s\n",
162*4882a593Smuzhiyun 			msixe[i].vector, name);
163*4882a593Smuzhiyun 		return ret;
164*4882a593Smuzhiyun 	}
165*4882a593Smuzhiyun 	return ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
adf_free_irqs(struct adf_accel_dev * accel_dev)168*4882a593Smuzhiyun static void adf_free_irqs(struct adf_accel_dev *accel_dev)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
171*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
172*4882a593Smuzhiyun 	struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
173*4882a593Smuzhiyun 	struct adf_etr_data *etr_data = accel_dev->transport;
174*4882a593Smuzhiyun 	int i = 0;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	if (pci_dev_info->msix_entries.num_entries > 1) {
177*4882a593Smuzhiyun 		for (i = 0; i < hw_data->num_banks; i++) {
178*4882a593Smuzhiyun 			irq_set_affinity_hint(msixe[i].vector, NULL);
179*4882a593Smuzhiyun 			free_irq(msixe[i].vector, &etr_data->banks[i]);
180*4882a593Smuzhiyun 		}
181*4882a593Smuzhiyun 	}
182*4882a593Smuzhiyun 	irq_set_affinity_hint(msixe[i].vector, NULL);
183*4882a593Smuzhiyun 	free_irq(msixe[i].vector, accel_dev);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
adf_isr_alloc_msix_entry_table(struct adf_accel_dev * accel_dev)186*4882a593Smuzhiyun static int adf_isr_alloc_msix_entry_table(struct adf_accel_dev *accel_dev)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	int i;
189*4882a593Smuzhiyun 	char **names;
190*4882a593Smuzhiyun 	struct msix_entry *entries;
191*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
192*4882a593Smuzhiyun 	u32 msix_num_entries = 1;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* If SR-IOV is disabled (vf_info is NULL), add entries for each bank */
195*4882a593Smuzhiyun 	if (!accel_dev->pf.vf_info)
196*4882a593Smuzhiyun 		msix_num_entries += hw_data->num_banks;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	entries = kcalloc_node(msix_num_entries, sizeof(*entries),
199*4882a593Smuzhiyun 			       GFP_KERNEL, dev_to_node(&GET_DEV(accel_dev)));
200*4882a593Smuzhiyun 	if (!entries)
201*4882a593Smuzhiyun 		return -ENOMEM;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	names = kcalloc(msix_num_entries, sizeof(char *), GFP_KERNEL);
204*4882a593Smuzhiyun 	if (!names) {
205*4882a593Smuzhiyun 		kfree(entries);
206*4882a593Smuzhiyun 		return -ENOMEM;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 	for (i = 0; i < msix_num_entries; i++) {
209*4882a593Smuzhiyun 		*(names + i) = kzalloc(ADF_MAX_MSIX_VECTOR_NAME, GFP_KERNEL);
210*4882a593Smuzhiyun 		if (!(*(names + i)))
211*4882a593Smuzhiyun 			goto err;
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 	accel_dev->accel_pci_dev.msix_entries.num_entries = msix_num_entries;
214*4882a593Smuzhiyun 	accel_dev->accel_pci_dev.msix_entries.entries = entries;
215*4882a593Smuzhiyun 	accel_dev->accel_pci_dev.msix_entries.names = names;
216*4882a593Smuzhiyun 	return 0;
217*4882a593Smuzhiyun err:
218*4882a593Smuzhiyun 	for (i = 0; i < msix_num_entries; i++)
219*4882a593Smuzhiyun 		kfree(*(names + i));
220*4882a593Smuzhiyun 	kfree(entries);
221*4882a593Smuzhiyun 	kfree(names);
222*4882a593Smuzhiyun 	return -ENOMEM;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
adf_isr_free_msix_entry_table(struct adf_accel_dev * accel_dev)225*4882a593Smuzhiyun static void adf_isr_free_msix_entry_table(struct adf_accel_dev *accel_dev)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	char **names = accel_dev->accel_pci_dev.msix_entries.names;
228*4882a593Smuzhiyun 	int i;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	kfree(accel_dev->accel_pci_dev.msix_entries.entries);
231*4882a593Smuzhiyun 	for (i = 0; i < accel_dev->accel_pci_dev.msix_entries.num_entries; i++)
232*4882a593Smuzhiyun 		kfree(*(names + i));
233*4882a593Smuzhiyun 	kfree(names);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
adf_setup_bh(struct adf_accel_dev * accel_dev)236*4882a593Smuzhiyun static int adf_setup_bh(struct adf_accel_dev *accel_dev)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	struct adf_etr_data *priv_data = accel_dev->transport;
239*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
240*4882a593Smuzhiyun 	int i;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	for (i = 0; i < hw_data->num_banks; i++)
243*4882a593Smuzhiyun 		tasklet_init(&priv_data->banks[i].resp_handler,
244*4882a593Smuzhiyun 			     adf_response_handler,
245*4882a593Smuzhiyun 			     (unsigned long)&priv_data->banks[i]);
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
adf_cleanup_bh(struct adf_accel_dev * accel_dev)249*4882a593Smuzhiyun static void adf_cleanup_bh(struct adf_accel_dev *accel_dev)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	struct adf_etr_data *priv_data = accel_dev->transport;
252*4882a593Smuzhiyun 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
253*4882a593Smuzhiyun 	int i;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	for (i = 0; i < hw_data->num_banks; i++) {
256*4882a593Smuzhiyun 		tasklet_disable(&priv_data->banks[i].resp_handler);
257*4882a593Smuzhiyun 		tasklet_kill(&priv_data->banks[i].resp_handler);
258*4882a593Smuzhiyun 	}
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun /**
262*4882a593Smuzhiyun  * adf_isr_resource_free() - Free IRQ for acceleration device
263*4882a593Smuzhiyun  * @accel_dev:  Pointer to acceleration device.
264*4882a593Smuzhiyun  *
265*4882a593Smuzhiyun  * Function frees interrupts for acceleration device.
266*4882a593Smuzhiyun  */
adf_isr_resource_free(struct adf_accel_dev * accel_dev)267*4882a593Smuzhiyun void adf_isr_resource_free(struct adf_accel_dev *accel_dev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	adf_free_irqs(accel_dev);
270*4882a593Smuzhiyun 	adf_cleanup_bh(accel_dev);
271*4882a593Smuzhiyun 	adf_disable_msix(&accel_dev->accel_pci_dev);
272*4882a593Smuzhiyun 	adf_isr_free_msix_entry_table(accel_dev);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(adf_isr_resource_free);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun /**
277*4882a593Smuzhiyun  * adf_isr_resource_alloc() - Allocate IRQ for acceleration device
278*4882a593Smuzhiyun  * @accel_dev:  Pointer to acceleration device.
279*4882a593Smuzhiyun  *
280*4882a593Smuzhiyun  * Function allocates interrupts for acceleration device.
281*4882a593Smuzhiyun  *
282*4882a593Smuzhiyun  * Return: 0 on success, error code otherwise.
283*4882a593Smuzhiyun  */
adf_isr_resource_alloc(struct adf_accel_dev * accel_dev)284*4882a593Smuzhiyun int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	int ret;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	ret = adf_isr_alloc_msix_entry_table(accel_dev);
289*4882a593Smuzhiyun 	if (ret)
290*4882a593Smuzhiyun 		goto err_out;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	ret = adf_enable_msix(accel_dev);
293*4882a593Smuzhiyun 	if (ret)
294*4882a593Smuzhiyun 		goto err_free_msix_table;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	ret = adf_setup_bh(accel_dev);
297*4882a593Smuzhiyun 	if (ret)
298*4882a593Smuzhiyun 		goto err_disable_msix;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	ret = adf_request_irqs(accel_dev);
301*4882a593Smuzhiyun 	if (ret)
302*4882a593Smuzhiyun 		goto err_cleanup_bh;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	return 0;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun err_cleanup_bh:
307*4882a593Smuzhiyun 	adf_cleanup_bh(accel_dev);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun err_disable_msix:
310*4882a593Smuzhiyun 	adf_disable_msix(&accel_dev->accel_pci_dev);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun err_free_msix_table:
313*4882a593Smuzhiyun 	adf_isr_free_msix_entry_table(accel_dev);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun err_out:
316*4882a593Smuzhiyun 	return ret;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(adf_isr_resource_alloc);
319