1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2010 Picochip Ltd., Jamie Iles 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __PICOXCELL_CRYPTO_REGS_H__ 6*4882a593Smuzhiyun #define __PICOXCELL_CRYPTO_REGS_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define SPA_STATUS_OK 0 9*4882a593Smuzhiyun #define SPA_STATUS_ICV_FAIL 1 10*4882a593Smuzhiyun #define SPA_STATUS_MEMORY_ERROR 2 11*4882a593Smuzhiyun #define SPA_STATUS_BLOCK_ERROR 3 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SPA_IRQ_CTRL_STAT_CNT_OFFSET 16 14*4882a593Smuzhiyun #define SPA_IRQ_STAT_STAT_MASK (1 << 4) 15*4882a593Smuzhiyun #define SPA_FIFO_STAT_STAT_OFFSET 16 16*4882a593Smuzhiyun #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET) 17*4882a593Smuzhiyun #define SPA_STATUS_RES_CODE_OFFSET 24 18*4882a593Smuzhiyun #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET) 19*4882a593Smuzhiyun #define SPA_KEY_SZ_CTX_INDEX_OFFSET 8 20*4882a593Smuzhiyun #define SPA_KEY_SZ_CIPHER_OFFSET 31 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SPA_IRQ_EN_REG_OFFSET 0x00000000 23*4882a593Smuzhiyun #define SPA_IRQ_STAT_REG_OFFSET 0x00000004 24*4882a593Smuzhiyun #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008 25*4882a593Smuzhiyun #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C 26*4882a593Smuzhiyun #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010 27*4882a593Smuzhiyun #define SPA_SRC_PTR_REG_OFFSET 0x00000020 28*4882a593Smuzhiyun #define SPA_DST_PTR_REG_OFFSET 0x00000024 29*4882a593Smuzhiyun #define SPA_OFFSET_REG_OFFSET 0x00000028 30*4882a593Smuzhiyun #define SPA_AAD_LEN_REG_OFFSET 0x0000002C 31*4882a593Smuzhiyun #define SPA_PROC_LEN_REG_OFFSET 0x00000030 32*4882a593Smuzhiyun #define SPA_ICV_LEN_REG_OFFSET 0x00000034 33*4882a593Smuzhiyun #define SPA_ICV_OFFSET_REG_OFFSET 0x00000038 34*4882a593Smuzhiyun #define SPA_SW_CTRL_REG_OFFSET 0x0000003C 35*4882a593Smuzhiyun #define SPA_CTRL_REG_OFFSET 0x00000040 36*4882a593Smuzhiyun #define SPA_AUX_INFO_REG_OFFSET 0x0000004C 37*4882a593Smuzhiyun #define SPA_STAT_POP_REG_OFFSET 0x00000050 38*4882a593Smuzhiyun #define SPA_STATUS_REG_OFFSET 0x00000054 39*4882a593Smuzhiyun #define SPA_KEY_SZ_REG_OFFSET 0x00000100 40*4882a593Smuzhiyun #define SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000 41*4882a593Smuzhiyun #define SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000 42*4882a593Smuzhiyun #define SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define SPA_IRQ_EN_REG_RESET 0x00000000 45*4882a593Smuzhiyun #define SPA_IRQ_CTRL_REG_RESET 0x00000000 46*4882a593Smuzhiyun #define SPA_FIFO_STAT_REG_RESET 0x00000000 47*4882a593Smuzhiyun #define SPA_SDMA_BRST_SZ_REG_RESET 0x00000000 48*4882a593Smuzhiyun #define SPA_SRC_PTR_REG_RESET 0x00000000 49*4882a593Smuzhiyun #define SPA_DST_PTR_REG_RESET 0x00000000 50*4882a593Smuzhiyun #define SPA_OFFSET_REG_RESET 0x00000000 51*4882a593Smuzhiyun #define SPA_AAD_LEN_REG_RESET 0x00000000 52*4882a593Smuzhiyun #define SPA_PROC_LEN_REG_RESET 0x00000000 53*4882a593Smuzhiyun #define SPA_ICV_LEN_REG_RESET 0x00000000 54*4882a593Smuzhiyun #define SPA_ICV_OFFSET_REG_RESET 0x00000000 55*4882a593Smuzhiyun #define SPA_SW_CTRL_REG_RESET 0x00000000 56*4882a593Smuzhiyun #define SPA_CTRL_REG_RESET 0x00000000 57*4882a593Smuzhiyun #define SPA_AUX_INFO_REG_RESET 0x00000000 58*4882a593Smuzhiyun #define SPA_STAT_POP_REG_RESET 0x00000000 59*4882a593Smuzhiyun #define SPA_STATUS_REG_RESET 0x00000000 60*4882a593Smuzhiyun #define SPA_KEY_SZ_REG_RESET 0x00000000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_IDX 4 63*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_IDX 8 64*4882a593Smuzhiyun #define SPA_CTRL_HASH_MODE_IDX 12 65*4882a593Smuzhiyun #define SPA_CTRL_CTX_IDX 16 66*4882a593Smuzhiyun #define SPA_CTRL_ENCRYPT_IDX 24 67*4882a593Smuzhiyun #define SPA_CTRL_AAD_COPY 25 68*4882a593Smuzhiyun #define SPA_CTRL_ICV_PT 26 69*4882a593Smuzhiyun #define SPA_CTRL_ICV_ENC 27 70*4882a593Smuzhiyun #define SPA_CTRL_ICV_APPEND 28 71*4882a593Smuzhiyun #define SPA_CTRL_KEY_EXP 29 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define SPA_KEY_SZ_CXT_IDX 8 74*4882a593Smuzhiyun #define SPA_KEY_SZ_CIPHER_IDX 31 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define SPA_IRQ_EN_CMD0_EN (1 << 0) 77*4882a593Smuzhiyun #define SPA_IRQ_EN_STAT_EN (1 << 4) 78*4882a593Smuzhiyun #define SPA_IRQ_EN_GLBL_EN (1 << 31) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_NULL 0x00 81*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_DES 0x01 82*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_AES 0x02 83*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_RC4 0x03 84*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_MULTI2 0x04 85*4882a593Smuzhiyun #define SPA_CTRL_CIPH_ALG_KASUMI 0x05 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX) 88*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX) 89*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX) 90*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX) 91*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX) 92*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX) 93*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX) 94*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX) 95*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX) 96*4882a593Smuzhiyun #define SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX) 99*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX) 100*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX) 101*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX) 102*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX) 103*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX) 104*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX) 105*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX) 106*4882a593Smuzhiyun #define SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX) 109*4882a593Smuzhiyun #define SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX) 110*4882a593Smuzhiyun #define SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define SPA_FIFO_STAT_EMPTY (1 << 31) 113*4882a593Smuzhiyun #define SPA_FIFO_CMD_FULL (1 << 7) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #endif /* __PICOXCELL_CRYPTO_REGS_H__ */ 116