xref: /OK3568_Linux_fs/kernel/drivers/crypto/nx/nx-842.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun #ifndef __NX_842_H__
4*4882a593Smuzhiyun #define __NX_842_H__
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/crypto.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/mm.h>
14*4882a593Smuzhiyun #include <linux/ratelimit.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* Restrictions on Data Descriptor List (DDL) and Entry (DDE) buffers
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * From NX P8 workbook, sec 4.9.1 "842 details"
19*4882a593Smuzhiyun  *   Each DDE buffer is 128 byte aligned
20*4882a593Smuzhiyun  *   Each DDE buffer size is a multiple of 32 bytes (except the last)
21*4882a593Smuzhiyun  *   The last DDE buffer size is a multiple of 8 bytes
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun #define DDE_BUFFER_ALIGN	(128)
24*4882a593Smuzhiyun #define DDE_BUFFER_SIZE_MULT	(32)
25*4882a593Smuzhiyun #define DDE_BUFFER_LAST_MULT	(8)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Arbitrary DDL length limit
28*4882a593Smuzhiyun  * Allows max buffer size of MAX-1 to MAX pages
29*4882a593Smuzhiyun  * (depending on alignment)
30*4882a593Smuzhiyun  */
31*4882a593Smuzhiyun #define DDL_LEN_MAX		(17)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* CCW 842 CI/FC masks
34*4882a593Smuzhiyun  * NX P8 workbook, section 4.3.1, figure 4-6
35*4882a593Smuzhiyun  * "CI/FC Boundary by NX CT type"
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun #define CCW_CI_842		(0x00003ff8)
38*4882a593Smuzhiyun #define CCW_FC_842		(0x00000007)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* CCW Function Codes (FC) for 842
41*4882a593Smuzhiyun  * NX P8 workbook, section 4.9, table 4-28
42*4882a593Smuzhiyun  * "Function Code Definitions for 842 Memory Compression"
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun #define CCW_FC_842_COMP_NOCRC	(0)
45*4882a593Smuzhiyun #define CCW_FC_842_COMP_CRC	(1)
46*4882a593Smuzhiyun #define CCW_FC_842_DECOMP_NOCRC	(2)
47*4882a593Smuzhiyun #define CCW_FC_842_DECOMP_CRC	(3)
48*4882a593Smuzhiyun #define CCW_FC_842_MOVE		(4)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* CSB CC Error Types for 842
51*4882a593Smuzhiyun  * NX P8 workbook, section 4.10.3, table 4-30
52*4882a593Smuzhiyun  * "Reported Error Types Summary Table"
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun /* These are all duplicates of existing codes defined in icswx.h. */
55*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP1	(80)
56*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP2	(82)
57*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP3	(84)
58*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP4	(86)
59*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP5	(92)
60*4882a593Smuzhiyun #define CSB_CC_TRANSLATION_DUP6	(94)
61*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP1	(81)
62*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP2	(83)
63*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP3	(85)
64*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP4	(87)
65*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP5	(93)
66*4882a593Smuzhiyun #define CSB_CC_PROTECTION_DUP6	(95)
67*4882a593Smuzhiyun #define CSB_CC_RD_EXTERNAL_DUP1	(89)
68*4882a593Smuzhiyun #define CSB_CC_RD_EXTERNAL_DUP2	(90)
69*4882a593Smuzhiyun #define CSB_CC_RD_EXTERNAL_DUP3	(91)
70*4882a593Smuzhiyun /* These are specific to NX */
71*4882a593Smuzhiyun /* 842 codes */
72*4882a593Smuzhiyun #define CSB_CC_TPBC_GT_SPBC	(64) /* no error, but >1 comp ratio */
73*4882a593Smuzhiyun #define CSB_CC_CRC_MISMATCH	(65) /* decomp crc mismatch */
74*4882a593Smuzhiyun #define CSB_CC_TEMPL_INVALID	(66) /* decomp invalid template value */
75*4882a593Smuzhiyun #define CSB_CC_TEMPL_OVERFLOW	(67) /* decomp template shows data after end */
76*4882a593Smuzhiyun /* sym crypt codes */
77*4882a593Smuzhiyun #define CSB_CC_DECRYPT_OVERFLOW	(64)
78*4882a593Smuzhiyun /* asym crypt codes */
79*4882a593Smuzhiyun #define CSB_CC_MINV_OVERFLOW	(128)
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun  * HW error - Job did not finish in the maximum time allowed.
82*4882a593Smuzhiyun  * Job terminated.
83*4882a593Smuzhiyun  */
84*4882a593Smuzhiyun #define CSB_CC_HW_EXPIRED_TIMER		(224)
85*4882a593Smuzhiyun /* These are reserved for hypervisor use */
86*4882a593Smuzhiyun #define CSB_CC_HYP_RESERVE_START	(240)
87*4882a593Smuzhiyun #define CSB_CC_HYP_RESERVE_END		(253)
88*4882a593Smuzhiyun #define CSB_CC_HYP_RESERVE_P9_END	(251)
89*4882a593Smuzhiyun /* No valid interrupt server (P9 or later). */
90*4882a593Smuzhiyun #define CSB_CC_HYP_RESERVE_NO_INTR_SERVER	(252)
91*4882a593Smuzhiyun #define CSB_CC_HYP_NO_HW		(254)
92*4882a593Smuzhiyun #define CSB_CC_HYP_HANG_ABORTED		(255)
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* CCB Completion Modes (CM) for 842
95*4882a593Smuzhiyun  * NX P8 workbook, section 4.3, figure 4-5
96*4882a593Smuzhiyun  * "CRB Details - Normal Cop_Req (CL=00, C=1)"
97*4882a593Smuzhiyun  */
98*4882a593Smuzhiyun #define CCB_CM_EXTRA_WRITE	(CCB_CM0_ALL_COMPLETIONS & CCB_CM12_STORE)
99*4882a593Smuzhiyun #define CCB_CM_INTERRUPT	(CCB_CM0_ALL_COMPLETIONS & CCB_CM12_INTERRUPT)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun #define LEN_ON_SIZE(pa, size)	((size) - ((pa) & ((size) - 1)))
102*4882a593Smuzhiyun #define LEN_ON_PAGE(pa)		LEN_ON_SIZE(pa, PAGE_SIZE)
103*4882a593Smuzhiyun 
nx842_get_pa(void * addr)104*4882a593Smuzhiyun static inline unsigned long nx842_get_pa(void *addr)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	if (!is_vmalloc_addr(addr))
107*4882a593Smuzhiyun 		return __pa(addr);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /**
113*4882a593Smuzhiyun  * This provides the driver's constraints.  Different nx842 implementations
114*4882a593Smuzhiyun  * may have varying requirements.  The constraints are:
115*4882a593Smuzhiyun  *   @alignment:	All buffers should be aligned to this
116*4882a593Smuzhiyun  *   @multiple:		All buffer lengths should be a multiple of this
117*4882a593Smuzhiyun  *   @minimum:		Buffer lengths must not be less than this amount
118*4882a593Smuzhiyun  *   @maximum:		Buffer lengths must not be more than this amount
119*4882a593Smuzhiyun  *
120*4882a593Smuzhiyun  * The constraints apply to all buffers and lengths, both input and output,
121*4882a593Smuzhiyun  * for both compression and decompression, except for the minimum which
122*4882a593Smuzhiyun  * only applies to compression input and decompression output; the
123*4882a593Smuzhiyun  * compressed data can be less than the minimum constraint.  It can be
124*4882a593Smuzhiyun  * assumed that compressed data will always adhere to the multiple
125*4882a593Smuzhiyun  * constraint.
126*4882a593Smuzhiyun  *
127*4882a593Smuzhiyun  * The driver may succeed even if these constraints are violated;
128*4882a593Smuzhiyun  * however the driver can return failure or suffer reduced performance
129*4882a593Smuzhiyun  * if any constraint is not met.
130*4882a593Smuzhiyun  */
131*4882a593Smuzhiyun struct nx842_constraints {
132*4882a593Smuzhiyun 	int alignment;
133*4882a593Smuzhiyun 	int multiple;
134*4882a593Smuzhiyun 	int minimum;
135*4882a593Smuzhiyun 	int maximum;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun struct nx842_driver {
139*4882a593Smuzhiyun 	char *name;
140*4882a593Smuzhiyun 	struct module *owner;
141*4882a593Smuzhiyun 	size_t workmem_size;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	struct nx842_constraints *constraints;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	int (*compress)(const unsigned char *in, unsigned int in_len,
146*4882a593Smuzhiyun 			unsigned char *out, unsigned int *out_len,
147*4882a593Smuzhiyun 			void *wrkmem);
148*4882a593Smuzhiyun 	int (*decompress)(const unsigned char *in, unsigned int in_len,
149*4882a593Smuzhiyun 			  unsigned char *out, unsigned int *out_len,
150*4882a593Smuzhiyun 			  void *wrkmem);
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun struct nx842_crypto_header_group {
154*4882a593Smuzhiyun 	__be16 padding;			/* unused bytes at start of group */
155*4882a593Smuzhiyun 	__be32 compressed_length;	/* compressed bytes in group */
156*4882a593Smuzhiyun 	__be32 uncompressed_length;	/* bytes after decompression */
157*4882a593Smuzhiyun } __packed;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun struct nx842_crypto_header {
160*4882a593Smuzhiyun 	__be16 magic;		/* NX842_CRYPTO_MAGIC */
161*4882a593Smuzhiyun 	__be16 ignore;		/* decompressed end bytes to ignore */
162*4882a593Smuzhiyun 	u8 groups;		/* total groups in this header */
163*4882a593Smuzhiyun 	struct nx842_crypto_header_group group[];
164*4882a593Smuzhiyun } __packed;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define NX842_CRYPTO_GROUP_MAX	(0x20)
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun struct nx842_crypto_ctx {
169*4882a593Smuzhiyun 	spinlock_t lock;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	u8 *wmem;
172*4882a593Smuzhiyun 	u8 *sbounce, *dbounce;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	struct nx842_crypto_header header;
175*4882a593Smuzhiyun 	struct nx842_crypto_header_group group[NX842_CRYPTO_GROUP_MAX];
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	struct nx842_driver *driver;
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun int nx842_crypto_init(struct crypto_tfm *tfm, struct nx842_driver *driver);
181*4882a593Smuzhiyun void nx842_crypto_exit(struct crypto_tfm *tfm);
182*4882a593Smuzhiyun int nx842_crypto_compress(struct crypto_tfm *tfm,
183*4882a593Smuzhiyun 			  const u8 *src, unsigned int slen,
184*4882a593Smuzhiyun 			  u8 *dst, unsigned int *dlen);
185*4882a593Smuzhiyun int nx842_crypto_decompress(struct crypto_tfm *tfm,
186*4882a593Smuzhiyun 			    const u8 *src, unsigned int slen,
187*4882a593Smuzhiyun 			    u8 *dst, unsigned int *dlen);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #endif /* __NX_842_H__ */
190