1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _N2_CORE_H 3*4882a593Smuzhiyun #define _N2_CORE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct ino_blob { 8*4882a593Smuzhiyun u64 intr; 9*4882a593Smuzhiyun u64 ino; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct spu_mdesc_info { 13*4882a593Smuzhiyun u64 cfg_handle; 14*4882a593Smuzhiyun struct ino_blob *ino_table; 15*4882a593Smuzhiyun int num_intrs; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct n2_crypto { 19*4882a593Smuzhiyun struct spu_mdesc_info cwq_info; 20*4882a593Smuzhiyun struct list_head cwq_list; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct n2_mau { 24*4882a593Smuzhiyun struct spu_mdesc_info mau_info; 25*4882a593Smuzhiyun struct list_head mau_list; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CWQ_ENTRY_SIZE 64 29*4882a593Smuzhiyun #define CWQ_NUM_ENTRIES 64 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MAU_ENTRY_SIZE 64 32*4882a593Smuzhiyun #define MAU_NUM_ENTRIES 64 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct cwq_initial_entry { 35*4882a593Smuzhiyun u64 control; 36*4882a593Smuzhiyun u64 src_addr; 37*4882a593Smuzhiyun u64 auth_key_addr; 38*4882a593Smuzhiyun u64 auth_iv_addr; 39*4882a593Smuzhiyun u64 final_auth_state_addr; 40*4882a593Smuzhiyun u64 enc_key_addr; 41*4882a593Smuzhiyun u64 enc_iv_addr; 42*4882a593Smuzhiyun u64 dest_addr; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct cwq_ext_entry { 46*4882a593Smuzhiyun u64 len; 47*4882a593Smuzhiyun u64 src_addr; 48*4882a593Smuzhiyun u64 resv1; 49*4882a593Smuzhiyun u64 resv2; 50*4882a593Smuzhiyun u64 resv3; 51*4882a593Smuzhiyun u64 resv4; 52*4882a593Smuzhiyun u64 resv5; 53*4882a593Smuzhiyun u64 resv6; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct cwq_final_entry { 57*4882a593Smuzhiyun u64 control; 58*4882a593Smuzhiyun u64 src_addr; 59*4882a593Smuzhiyun u64 resv1; 60*4882a593Smuzhiyun u64 resv2; 61*4882a593Smuzhiyun u64 resv3; 62*4882a593Smuzhiyun u64 resv4; 63*4882a593Smuzhiyun u64 resv5; 64*4882a593Smuzhiyun u64 resv6; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONTROL_LEN 0x000000000000ffffULL 68*4882a593Smuzhiyun #define CONTROL_LEN_SHIFT 0 69*4882a593Smuzhiyun #define CONTROL_HMAC_KEY_LEN 0x0000000000ff0000ULL 70*4882a593Smuzhiyun #define CONTROL_HMAC_KEY_LEN_SHIFT 16 71*4882a593Smuzhiyun #define CONTROL_ENC_TYPE 0x00000000ff000000ULL 72*4882a593Smuzhiyun #define CONTROL_ENC_TYPE_SHIFT 24 73*4882a593Smuzhiyun #define ENC_TYPE_ALG_RC4_STREAM 0x00ULL 74*4882a593Smuzhiyun #define ENC_TYPE_ALG_RC4_NOSTREAM 0x04ULL 75*4882a593Smuzhiyun #define ENC_TYPE_ALG_DES 0x08ULL 76*4882a593Smuzhiyun #define ENC_TYPE_ALG_3DES 0x0cULL 77*4882a593Smuzhiyun #define ENC_TYPE_ALG_AES128 0x10ULL 78*4882a593Smuzhiyun #define ENC_TYPE_ALG_AES192 0x14ULL 79*4882a593Smuzhiyun #define ENC_TYPE_ALG_AES256 0x18ULL 80*4882a593Smuzhiyun #define ENC_TYPE_ALG_RESERVED 0x1cULL 81*4882a593Smuzhiyun #define ENC_TYPE_ALG_MASK 0x1cULL 82*4882a593Smuzhiyun #define ENC_TYPE_CHAINING_ECB 0x00ULL 83*4882a593Smuzhiyun #define ENC_TYPE_CHAINING_CBC 0x01ULL 84*4882a593Smuzhiyun #define ENC_TYPE_CHAINING_CFB 0x02ULL 85*4882a593Smuzhiyun #define ENC_TYPE_CHAINING_COUNTER 0x03ULL 86*4882a593Smuzhiyun #define ENC_TYPE_CHAINING_MASK 0x03ULL 87*4882a593Smuzhiyun #define CONTROL_AUTH_TYPE 0x0000001f00000000ULL 88*4882a593Smuzhiyun #define CONTROL_AUTH_TYPE_SHIFT 32 89*4882a593Smuzhiyun #define AUTH_TYPE_RESERVED 0x00ULL 90*4882a593Smuzhiyun #define AUTH_TYPE_MD5 0x01ULL 91*4882a593Smuzhiyun #define AUTH_TYPE_SHA1 0x02ULL 92*4882a593Smuzhiyun #define AUTH_TYPE_SHA256 0x03ULL 93*4882a593Smuzhiyun #define AUTH_TYPE_CRC32 0x04ULL 94*4882a593Smuzhiyun #define AUTH_TYPE_HMAC_MD5 0x05ULL 95*4882a593Smuzhiyun #define AUTH_TYPE_HMAC_SHA1 0x06ULL 96*4882a593Smuzhiyun #define AUTH_TYPE_HMAC_SHA256 0x07ULL 97*4882a593Smuzhiyun #define AUTH_TYPE_TCP_CHECKSUM 0x08ULL 98*4882a593Smuzhiyun #define AUTH_TYPE_SSL_HMAC_MD5 0x09ULL 99*4882a593Smuzhiyun #define AUTH_TYPE_SSL_HMAC_SHA1 0x0aULL 100*4882a593Smuzhiyun #define AUTH_TYPE_SSL_HMAC_SHA256 0x0bULL 101*4882a593Smuzhiyun #define CONTROL_STRAND 0x000000e000000000ULL 102*4882a593Smuzhiyun #define CONTROL_STRAND_SHIFT 37 103*4882a593Smuzhiyun #define CONTROL_HASH_LEN 0x0000ff0000000000ULL 104*4882a593Smuzhiyun #define CONTROL_HASH_LEN_SHIFT 40 105*4882a593Smuzhiyun #define CONTROL_INTERRUPT 0x0001000000000000ULL 106*4882a593Smuzhiyun #define CONTROL_STORE_FINAL_AUTH_STATE 0x0002000000000000ULL 107*4882a593Smuzhiyun #define CONTROL_RESERVED 0x001c000000000000ULL 108*4882a593Smuzhiyun #define CONTROL_HV_DONE 0x0004000000000000ULL 109*4882a593Smuzhiyun #define CONTROL_HV_PROTOCOL_ERROR 0x0008000000000000ULL 110*4882a593Smuzhiyun #define CONTROL_HV_HARDWARE_ERROR 0x0010000000000000ULL 111*4882a593Smuzhiyun #define CONTROL_END_OF_BLOCK 0x0020000000000000ULL 112*4882a593Smuzhiyun #define CONTROL_START_OF_BLOCK 0x0040000000000000ULL 113*4882a593Smuzhiyun #define CONTROL_ENCRYPT 0x0080000000000000ULL 114*4882a593Smuzhiyun #define CONTROL_OPCODE 0xff00000000000000ULL 115*4882a593Smuzhiyun #define CONTROL_OPCODE_SHIFT 56 116*4882a593Smuzhiyun #define OPCODE_INPLACE_BIT 0x80ULL 117*4882a593Smuzhiyun #define OPCODE_SSL_KEYBLOCK 0x10ULL 118*4882a593Smuzhiyun #define OPCODE_COPY 0x20ULL 119*4882a593Smuzhiyun #define OPCODE_ENCRYPT 0x40ULL 120*4882a593Smuzhiyun #define OPCODE_AUTH_MAC 0x41ULL 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* !(__ASSEMBLY__) */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* NCS v2.0 hypervisor interfaces */ 125*4882a593Smuzhiyun #define HV_NCS_QTYPE_MAU 0x01 126*4882a593Smuzhiyun #define HV_NCS_QTYPE_CWQ 0x02 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* ncs_qconf() 129*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 130*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_QCONF 131*4882a593Smuzhiyun * ARG0: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) 132*4882a593Smuzhiyun * ARG1: Real address of queue, or handle for unconfigure 133*4882a593Smuzhiyun * ARG2: Number of entries in queue, zero for unconfigure 134*4882a593Smuzhiyun * RET0: status 135*4882a593Smuzhiyun * RET1: queue handle 136*4882a593Smuzhiyun * 137*4882a593Smuzhiyun * Configure a queue in the stream processing unit. 138*4882a593Smuzhiyun * 139*4882a593Smuzhiyun * The real address given as the base must be 64-byte 140*4882a593Smuzhiyun * aligned. 141*4882a593Smuzhiyun * 142*4882a593Smuzhiyun * The queue size can range from a minimum of 2 to a maximum 143*4882a593Smuzhiyun * of 64. The queue size must be a power of two. 144*4882a593Smuzhiyun * 145*4882a593Smuzhiyun * To unconfigure a queue, specify a length of zero and place 146*4882a593Smuzhiyun * the queue handle into ARG1. 147*4882a593Smuzhiyun * 148*4882a593Smuzhiyun * On configure success the hypervisor will set the FIRST, HEAD, 149*4882a593Smuzhiyun * and TAIL registers to the address of the first entry in the 150*4882a593Smuzhiyun * queue. The LAST register will be set to point to the last 151*4882a593Smuzhiyun * entry in the queue. 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun #define HV_FAST_NCS_QCONF 0x111 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* ncs_qinfo() 156*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 157*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_QINFO 158*4882a593Smuzhiyun * ARG0: Queue handle 159*4882a593Smuzhiyun * RET0: status 160*4882a593Smuzhiyun * RET1: Queue type (HV_NCS_QTYPE_{MAU,CWQ}) 161*4882a593Smuzhiyun * RET2: Queue base address 162*4882a593Smuzhiyun * RET3: Number of entries 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #define HV_FAST_NCS_QINFO 0x112 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* ncs_gethead() 167*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 168*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_GETHEAD 169*4882a593Smuzhiyun * ARG0: Queue handle 170*4882a593Smuzhiyun * RET0: status 171*4882a593Smuzhiyun * RET1: queue head offset 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun #define HV_FAST_NCS_GETHEAD 0x113 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* ncs_gettail() 176*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 177*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_GETTAIL 178*4882a593Smuzhiyun * ARG0: Queue handle 179*4882a593Smuzhiyun * RET0: status 180*4882a593Smuzhiyun * RET1: queue tail offset 181*4882a593Smuzhiyun */ 182*4882a593Smuzhiyun #define HV_FAST_NCS_GETTAIL 0x114 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* ncs_settail() 185*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 186*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_SETTAIL 187*4882a593Smuzhiyun * ARG0: Queue handle 188*4882a593Smuzhiyun * ARG1: New tail offset 189*4882a593Smuzhiyun * RET0: status 190*4882a593Smuzhiyun */ 191*4882a593Smuzhiyun #define HV_FAST_NCS_SETTAIL 0x115 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* ncs_qhandle_to_devino() 194*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 195*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_QHANDLE_TO_DEVINO 196*4882a593Smuzhiyun * ARG0: Queue handle 197*4882a593Smuzhiyun * RET0: status 198*4882a593Smuzhiyun * RET1: devino 199*4882a593Smuzhiyun */ 200*4882a593Smuzhiyun #define HV_FAST_NCS_QHANDLE_TO_DEVINO 0x116 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* ncs_sethead_marker() 203*4882a593Smuzhiyun * TRAP: HV_FAST_TRAP 204*4882a593Smuzhiyun * FUNCTION: HV_FAST_NCS_SETHEAD_MARKER 205*4882a593Smuzhiyun * ARG0: Queue handle 206*4882a593Smuzhiyun * ARG1: New head offset 207*4882a593Smuzhiyun * RET0: status 208*4882a593Smuzhiyun */ 209*4882a593Smuzhiyun #define HV_FAST_NCS_SETHEAD_MARKER 0x117 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 212*4882a593Smuzhiyun extern unsigned long sun4v_ncs_qconf(unsigned long queue_type, 213*4882a593Smuzhiyun unsigned long queue_ra, 214*4882a593Smuzhiyun unsigned long num_entries, 215*4882a593Smuzhiyun unsigned long *qhandle); 216*4882a593Smuzhiyun extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle, 217*4882a593Smuzhiyun unsigned long *queue_type, 218*4882a593Smuzhiyun unsigned long *queue_ra, 219*4882a593Smuzhiyun unsigned long *num_entries); 220*4882a593Smuzhiyun extern unsigned long sun4v_ncs_gethead(unsigned long qhandle, 221*4882a593Smuzhiyun unsigned long *head); 222*4882a593Smuzhiyun extern unsigned long sun4v_ncs_gettail(unsigned long qhandle, 223*4882a593Smuzhiyun unsigned long *tail); 224*4882a593Smuzhiyun extern unsigned long sun4v_ncs_settail(unsigned long qhandle, 225*4882a593Smuzhiyun unsigned long tail); 226*4882a593Smuzhiyun extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle, 227*4882a593Smuzhiyun unsigned long *devino); 228*4882a593Smuzhiyun extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle, 229*4882a593Smuzhiyun unsigned long head); 230*4882a593Smuzhiyun #endif /* !(__ASSEMBLY__) */ 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #endif /* _N2_CORE_H */ 233