1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * Marvell OcteonTX CPT driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2019 Marvell International Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 7*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __OTX_CPTPF_H 12*4882a593Smuzhiyun #define __OTX_CPTPF_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun #include <linux/device.h> 16*4882a593Smuzhiyun #include "otx_cptpf_ucode.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * OcteonTX CPT device structure 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun struct otx_cpt_device { 22*4882a593Smuzhiyun void __iomem *reg_base; /* Register start address */ 23*4882a593Smuzhiyun struct pci_dev *pdev; /* Pci device handle */ 24*4882a593Smuzhiyun struct otx_cpt_eng_grps eng_grps;/* Engine groups information */ 25*4882a593Smuzhiyun struct list_head list; 26*4882a593Smuzhiyun u8 pf_type; /* PF type SE or AE */ 27*4882a593Smuzhiyun u8 max_vfs; /* Maximum number of VFs supported by the CPT */ 28*4882a593Smuzhiyun u8 vfs_enabled; /* Number of enabled VFs */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx); 32*4882a593Smuzhiyun void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __OTX_CPTPF_H */ 35