1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/interrupt.h>
6*4882a593Smuzhiyun #include <linux/pm_runtime.h>
7*4882a593Smuzhiyun #include "cc_driver.h"
8*4882a593Smuzhiyun #include "cc_buffer_mgr.h"
9*4882a593Smuzhiyun #include "cc_request_mgr.h"
10*4882a593Smuzhiyun #include "cc_sram_mgr.h"
11*4882a593Smuzhiyun #include "cc_hash.h"
12*4882a593Smuzhiyun #include "cc_pm.h"
13*4882a593Smuzhiyun #include "cc_fips.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define POWER_DOWN_ENABLE 0x01
16*4882a593Smuzhiyun #define POWER_DOWN_DISABLE 0x00
17*4882a593Smuzhiyun
cc_pm_suspend(struct device * dev)18*4882a593Smuzhiyun static int cc_pm_suspend(struct device *dev)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct cc_drvdata *drvdata = dev_get_drvdata(dev);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
23*4882a593Smuzhiyun fini_cc_regs(drvdata);
24*4882a593Smuzhiyun cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
25*4882a593Smuzhiyun clk_disable_unprepare(drvdata->clk);
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
cc_pm_resume(struct device * dev)29*4882a593Smuzhiyun static int cc_pm_resume(struct device *dev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int rc;
32*4882a593Smuzhiyun struct cc_drvdata *drvdata = dev_get_drvdata(dev);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
35*4882a593Smuzhiyun /* Enables the device source clk */
36*4882a593Smuzhiyun rc = clk_prepare_enable(drvdata->clk);
37*4882a593Smuzhiyun if (rc) {
38*4882a593Smuzhiyun dev_err(dev, "failed getting clock back on. We're toast.\n");
39*4882a593Smuzhiyun return rc;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun /* wait for Cryptocell reset completion */
42*4882a593Smuzhiyun if (!cc_wait_for_reset_completion(drvdata)) {
43*4882a593Smuzhiyun dev_err(dev, "Cryptocell reset not completed");
44*4882a593Smuzhiyun return -EBUSY;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
48*4882a593Smuzhiyun rc = init_cc_regs(drvdata, false);
49*4882a593Smuzhiyun if (rc) {
50*4882a593Smuzhiyun dev_err(dev, "init_cc_regs (%x)\n", rc);
51*4882a593Smuzhiyun return rc;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun /* check if tee fips error occurred during power down */
54*4882a593Smuzhiyun cc_tee_handle_fips_error(drvdata);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun cc_init_hash_sram(drvdata);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun const struct dev_pm_ops ccree_pm = {
62*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(cc_pm_suspend, cc_pm_resume, NULL)
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
cc_pm_get(struct device * dev)65*4882a593Smuzhiyun int cc_pm_get(struct device *dev)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun int rc = pm_runtime_get_sync(dev);
68*4882a593Smuzhiyun if (rc < 0) {
69*4882a593Smuzhiyun pm_runtime_put_noidle(dev);
70*4882a593Smuzhiyun return rc;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
cc_pm_put_suspend(struct device * dev)76*4882a593Smuzhiyun void cc_pm_put_suspend(struct device *dev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun pm_runtime_mark_last_busy(dev);
79*4882a593Smuzhiyun pm_runtime_put_autosuspend(dev);
80*4882a593Smuzhiyun }
81