1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _CC_LLI_DEFS_H_ 5*4882a593Smuzhiyun #define _CC_LLI_DEFS_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/types.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Max DLLI size 10*4882a593Smuzhiyun * AKA CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #define DLLI_SIZE_BIT_SIZE 0x18 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CC_MAX_MLLI_ENTRY_SIZE 0xFFFF 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define LLI_MAX_NUM_OF_DATA_ENTRIES 128 17*4882a593Smuzhiyun #define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 8 18*4882a593Smuzhiyun #define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */ 19*4882a593Smuzhiyun #define MAX_NUM_OF_BUFFERS_IN_MLLI 4 20*4882a593Smuzhiyun #define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \ 21*4882a593Smuzhiyun (2 * LLI_MAX_NUM_OF_DATA_ENTRIES + \ 22*4882a593Smuzhiyun LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Size of entry */ 25*4882a593Smuzhiyun #define LLI_ENTRY_WORD_SIZE 2 26*4882a593Smuzhiyun #define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32)) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Word0[31:0] = ADDR[31:0] */ 29*4882a593Smuzhiyun #define LLI_WORD0_OFFSET 0 30*4882a593Smuzhiyun #define LLI_LADDR_BIT_OFFSET 0 31*4882a593Smuzhiyun #define LLI_LADDR_BIT_SIZE 32 32*4882a593Smuzhiyun /* Word1[31:16] = ADDR[47:32]; Word1[15:0] = SIZE */ 33*4882a593Smuzhiyun #define LLI_WORD1_OFFSET 1 34*4882a593Smuzhiyun #define LLI_SIZE_BIT_OFFSET 0 35*4882a593Smuzhiyun #define LLI_SIZE_BIT_SIZE 16 36*4882a593Smuzhiyun #define LLI_HADDR_BIT_OFFSET 16 37*4882a593Smuzhiyun #define LLI_HADDR_BIT_SIZE 16 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET) 40*4882a593Smuzhiyun #define LLI_HADDR_MASK GENMASK( \ 41*4882a593Smuzhiyun (LLI_HADDR_BIT_OFFSET + LLI_HADDR_BIT_SIZE - 1),\ 42*4882a593Smuzhiyun LLI_HADDR_BIT_OFFSET) 43*4882a593Smuzhiyun cc_lli_set_addr(u32 * lli_p,dma_addr_t addr)44*4882a593Smuzhiyunstatic inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX); 47*4882a593Smuzhiyun #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 48*4882a593Smuzhiyun lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK; 49*4882a593Smuzhiyun lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 32)); 50*4882a593Smuzhiyun #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun cc_lli_set_size(u32 * lli_p,u16 size)53*4882a593Smuzhiyunstatic inline void cc_lli_set_size(u32 *lli_p, u16 size) 54*4882a593Smuzhiyun { 55*4882a593Smuzhiyun lli_p[LLI_WORD1_OFFSET] &= ~LLI_SIZE_MASK; 56*4882a593Smuzhiyun lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_SIZE_MASK, size); 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /*_CC_LLI_DEFS_H_*/ 60