1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __CC_CRYS_KERNEL_H__ 5*4882a593Smuzhiyun #define __CC_CRYS_KERNEL_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun // -------------------------------------- 8*4882a593Smuzhiyun // BLOCK: DSCRPTR 9*4882a593Smuzhiyun // -------------------------------------- 10*4882a593Smuzhiyun #define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL 11*4882a593Smuzhiyun #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL 12*4882a593Smuzhiyun #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL 13*4882a593Smuzhiyun #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL 14*4882a593Smuzhiyun #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL 15*4882a593Smuzhiyun #define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL 16*4882a593Smuzhiyun #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL 17*4882a593Smuzhiyun #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL 18*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL 19*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL 20*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL 21*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL 22*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL 23*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL 24*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL 25*4882a593Smuzhiyun #define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL 26*4882a593Smuzhiyun #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL 27*4882a593Smuzhiyun #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL 28*4882a593Smuzhiyun #define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL 29*4882a593Smuzhiyun #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL 30*4882a593Smuzhiyun #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL 31*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL 32*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL 33*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL 34*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL 35*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL 36*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL 37*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL 38*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL 39*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL 40*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL 41*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL 42*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL 43*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL 44*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL 45*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL 46*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL 47*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL 48*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL 49*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL 50*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL 51*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL 52*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL 53*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL 54*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL 55*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL 56*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL 57*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL 58*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL 59*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL 60*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL 61*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL 62*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL 63*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL 64*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL 65*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL 66*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL 67*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL 68*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL 69*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL 70*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL 71*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL 72*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL 73*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL 74*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL 75*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL 76*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL 77*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL 78*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL 79*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL 80*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL 81*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL 82*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL 83*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL 84*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL 85*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL 86*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL 87*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL 88*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL 89*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL 90*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL 91*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL 92*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL 93*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL 94*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL 95*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL 96*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL 97*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL 98*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL 99*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL 100*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL 101*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL 102*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL 103*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL 104*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL 105*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL 106*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL 107*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL 108*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL 109*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL 110*4882a593Smuzhiyun #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL 111*4882a593Smuzhiyun // -------------------------------------- 112*4882a593Smuzhiyun // BLOCK: AXI_P 113*4882a593Smuzhiyun // -------------------------------------- 114*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL 115*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL 116*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL 117*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL 118*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL 119*4882a593Smuzhiyun #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL 120*4882a593Smuzhiyun #define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL 121*4882a593Smuzhiyun #define CC_AXIM_MON_COMP8_REG_OFFSET 0xBA0UL 122*4882a593Smuzhiyun #define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL 123*4882a593Smuzhiyun #define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL 124*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_REG_OFFSET 0xBC4UL 125*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL 126*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL 127*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL 128*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL 129*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL 130*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL 131*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL 132*4882a593Smuzhiyun #define CC_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL 133*4882a593Smuzhiyun #define CC_AXIM_CFG_REG_OFFSET 0xBE8UL 134*4882a593Smuzhiyun #define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL 135*4882a593Smuzhiyun #define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL 136*4882a593Smuzhiyun #define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL 137*4882a593Smuzhiyun #define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL 138*4882a593Smuzhiyun #define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL 139*4882a593Smuzhiyun #define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL 140*4882a593Smuzhiyun #define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL 141*4882a593Smuzhiyun #define CC_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL 142*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_REG_OFFSET 0xBECUL 143*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL 144*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL 145*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL 146*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL 147*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL 148*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL 149*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL 150*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL 151*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL 152*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL 153*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL 154*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL 155*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL 156*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL 157*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL 158*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL 159*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL 160*4882a593Smuzhiyun #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL 161*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL 162*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL 163*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL 164*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL 165*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL 166*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL 167*4882a593Smuzhiyun #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL 168*4882a593Smuzhiyun #endif // __CC_CRYS_KERNEL_H__ 169