1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __CC_HOST_H__ 5*4882a593Smuzhiyun #define __CC_HOST_H__ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun // -------------------------------------- 8*4882a593Smuzhiyun // BLOCK: HOST_P 9*4882a593Smuzhiyun // -------------------------------------- 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* IRR */ 13*4882a593Smuzhiyun #define CC_HOST_IRR_REG_OFFSET 0xA00UL 14*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT 0x1UL 15*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE 0x1UL 16*4882a593Smuzhiyun #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL 17*4882a593Smuzhiyun #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL 18*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL 19*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE 0x1UL 20*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT 0x4UL 21*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE 0x1UL 22*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT 0x5UL 23*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE 0x1UL 24*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT 0x6UL 25*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE 0x1UL 26*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT 0x7UL 27*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE 0x1UL 28*4882a593Smuzhiyun #define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL 29*4882a593Smuzhiyun #define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL 30*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT 0x9UL 31*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE 0x1UL 32*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0xAUL 33*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE 0x1UL 34*4882a593Smuzhiyun #define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL 35*4882a593Smuzhiyun #define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL 36*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT 0xCUL 37*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE 0x1UL 38*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT 0xDUL 39*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE 0x1UL 40*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT 0xEUL 41*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE 0x1UL 42*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT 0xFUL 43*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE 0x1UL 44*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT 0x10UL 45*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE 0x1UL 46*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT 0x11UL 47*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE 0x1UL 48*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT 0x12UL 49*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE 0x1UL 50*4882a593Smuzhiyun #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL 51*4882a593Smuzhiyun #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL 52*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT 0x14UL 53*4882a593Smuzhiyun #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE 0x1UL 54*4882a593Smuzhiyun #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL 55*4882a593Smuzhiyun #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL 56*4882a593Smuzhiyun #define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL 57*4882a593Smuzhiyun #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL 58*4882a593Smuzhiyun #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0xCUL 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* IMR */ 61*4882a593Smuzhiyun #define CC_HOST_IMR_REG_OFFSET 0x0A04UL 62*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT 0x1UL 63*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE 0x1UL 64*4882a593Smuzhiyun #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL 65*4882a593Smuzhiyun #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL 66*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT 0x3UL 67*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE 0x1UL 68*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT 0x4UL 69*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE 0x1UL 70*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT 0x5UL 71*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE 0x1UL 72*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT 0x6UL 73*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE 0x1UL 74*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT 0x7UL 75*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE 0x1UL 76*4882a593Smuzhiyun #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL 77*4882a593Smuzhiyun #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL 78*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT 0x9UL 79*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE 0x1UL 80*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT 0xAUL 81*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE 0x1UL 82*4882a593Smuzhiyun #define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL 83*4882a593Smuzhiyun #define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL 84*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT 0xCUL 85*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE 0x1UL 86*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT 0xDUL 87*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE 0x1UL 88*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT 0xEUL 89*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE 0x1UL 90*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT 0xFUL 91*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE 0x1UL 92*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT 0x10UL 93*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE 0x1UL 94*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT 0x11UL 95*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE 0x1UL 96*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT 0x12UL 97*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE 0x1UL 98*4882a593Smuzhiyun #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL 99*4882a593Smuzhiyun #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL 100*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT 0x14UL 101*4882a593Smuzhiyun #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE 0x1UL 102*4882a593Smuzhiyun #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL 103*4882a593Smuzhiyun #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* ICR */ 106*4882a593Smuzhiyun #define CC_HOST_ICR_REG_OFFSET 0xA08UL 107*4882a593Smuzhiyun #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL 108*4882a593Smuzhiyun #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL 109*4882a593Smuzhiyun #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL 110*4882a593Smuzhiyun #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL 111*4882a593Smuzhiyun #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL 112*4882a593Smuzhiyun #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL 113*4882a593Smuzhiyun #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL 114*4882a593Smuzhiyun #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL 115*4882a593Smuzhiyun #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL 116*4882a593Smuzhiyun #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL 117*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_REG_OFFSET 0x0A10UL 118*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 119*4882a593Smuzhiyun #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 120*4882a593Smuzhiyun #define CC_SECURITY_DISABLED_REG_OFFSET 0x0A1CUL 121*4882a593Smuzhiyun #define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT 0x0UL 122*4882a593Smuzhiyun #define CC_SECURITY_DISABLED_VALUE_BIT_SIZE 0x1UL 123*4882a593Smuzhiyun #define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL 124*4882a593Smuzhiyun #define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL 125*4882a593Smuzhiyun #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL 126*4882a593Smuzhiyun #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL 127*4882a593Smuzhiyun #define CC_HOST_BOOT_REG_OFFSET 0xA28UL 128*4882a593Smuzhiyun #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL 129*4882a593Smuzhiyun #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL 130*4882a593Smuzhiyun #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL 131*4882a593Smuzhiyun #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL 132*4882a593Smuzhiyun #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL 133*4882a593Smuzhiyun #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL 134*4882a593Smuzhiyun #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL 135*4882a593Smuzhiyun #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL 136*4882a593Smuzhiyun #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL 137*4882a593Smuzhiyun #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL 138*4882a593Smuzhiyun #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL 139*4882a593Smuzhiyun #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL 140*4882a593Smuzhiyun #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL 141*4882a593Smuzhiyun #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 142*4882a593Smuzhiyun #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL 143*4882a593Smuzhiyun #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL 144*4882a593Smuzhiyun #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL 145*4882a593Smuzhiyun #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL 146*4882a593Smuzhiyun #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL 147*4882a593Smuzhiyun #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL 148*4882a593Smuzhiyun #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL 149*4882a593Smuzhiyun #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL 150*4882a593Smuzhiyun #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL 151*4882a593Smuzhiyun #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL 152*4882a593Smuzhiyun #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL 153*4882a593Smuzhiyun #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL 154*4882a593Smuzhiyun #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL 155*4882a593Smuzhiyun #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL 156*4882a593Smuzhiyun #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL 157*4882a593Smuzhiyun #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL 158*4882a593Smuzhiyun #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL 159*4882a593Smuzhiyun #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL 160*4882a593Smuzhiyun #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL 161*4882a593Smuzhiyun #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL 162*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL 163*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 164*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL 165*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL 166*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL 167*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL 168*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL 169*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL 170*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL 171*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL 172*4882a593Smuzhiyun #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL 173*4882a593Smuzhiyun #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL 174*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL 175*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL 176*4882a593Smuzhiyun #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL 177*4882a593Smuzhiyun #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL 178*4882a593Smuzhiyun #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL 179*4882a593Smuzhiyun #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL 180*4882a593Smuzhiyun #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL 181*4882a593Smuzhiyun #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL 182*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL 183*4882a593Smuzhiyun #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL 184*4882a593Smuzhiyun #define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL 185*4882a593Smuzhiyun #define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL 186*4882a593Smuzhiyun #define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL 187*4882a593Smuzhiyun #define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL 188*4882a593Smuzhiyun #define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL 189*4882a593Smuzhiyun #define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL 190*4882a593Smuzhiyun #define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL 191*4882a593Smuzhiyun #define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL 192*4882a593Smuzhiyun #define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL 193*4882a593Smuzhiyun #define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL 194*4882a593Smuzhiyun #define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL 195*4882a593Smuzhiyun #define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL 196*4882a593Smuzhiyun #define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL 197*4882a593Smuzhiyun #define CC_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL 198*4882a593Smuzhiyun #define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL 199*4882a593Smuzhiyun #define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL 200*4882a593Smuzhiyun #define CC_HOST_GPR0_REG_OFFSET 0xA70UL 201*4882a593Smuzhiyun #define CC_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL 202*4882a593Smuzhiyun #define CC_HOST_GPR0_VALUE_BIT_SIZE 0x20UL 203*4882a593Smuzhiyun #define CC_GPR_HOST_REG_OFFSET 0xA74UL 204*4882a593Smuzhiyun #define CC_GPR_HOST_VALUE_BIT_SHIFT 0x0UL 205*4882a593Smuzhiyun #define CC_GPR_HOST_VALUE_BIT_SIZE 0x20UL 206*4882a593Smuzhiyun #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL 207*4882a593Smuzhiyun #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL 208*4882a593Smuzhiyun #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL 209*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET 0x0A7CUL 210*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT 0x0UL 211*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE 0x1UL 212*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT 0x1UL 213*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE 0x1UL 214*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT 0x2UL 215*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE 0x1UL 216*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT 0x3UL 217*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE 0x1UL 218*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT 0x4UL 219*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE 0x1UL 220*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT 0x5UL 221*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE 0x1UL 222*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT 0x6UL 223*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE 0x1UL 224*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT 0x7UL 225*4882a593Smuzhiyun #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE 0x1UL 226*4882a593Smuzhiyun // -------------------------------------- 227*4882a593Smuzhiyun // BLOCK: ID_REGISTERS 228*4882a593Smuzhiyun // -------------------------------------- 229*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_4_REG_OFFSET 0x0FD0UL 230*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT 0x0UL 231*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE 0x4UL 232*4882a593Smuzhiyun #define CC_PIDRESERVED0_REG_OFFSET 0x0FD4UL 233*4882a593Smuzhiyun #define CC_PIDRESERVED1_REG_OFFSET 0x0FD8UL 234*4882a593Smuzhiyun #define CC_PIDRESERVED2_REG_OFFSET 0x0FDCUL 235*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_0_REG_OFFSET 0x0FE0UL 236*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT 0x0UL 237*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE 0x8UL 238*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_1_REG_OFFSET 0x0FE4UL 239*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT 0x0UL 240*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE 0x4UL 241*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT 0x4UL 242*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE 0x4UL 243*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_REG_OFFSET 0x0FE8UL 244*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT 0x0UL 245*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE 0x3UL 246*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT 0x3UL 247*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE 0x1UL 248*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT 0x4UL 249*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE 0x4UL 250*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_3_REG_OFFSET 0x0FECUL 251*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT 0x0UL 252*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE 0x4UL 253*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT 0x4UL 254*4882a593Smuzhiyun #define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE 0x4UL 255*4882a593Smuzhiyun #define CC_COMPONENT_ID_0_REG_OFFSET 0x0FF0UL 256*4882a593Smuzhiyun #define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT 0x0UL 257*4882a593Smuzhiyun #define CC_COMPONENT_ID_0_VALUE_BIT_SIZE 0x8UL 258*4882a593Smuzhiyun #define CC_COMPONENT_ID_1_REG_OFFSET 0x0FF4UL 259*4882a593Smuzhiyun #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT 0x0UL 260*4882a593Smuzhiyun #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE 0x4UL 261*4882a593Smuzhiyun #define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT 0x4UL 262*4882a593Smuzhiyun #define CC_COMPONENT_ID_1_CLASS_BIT_SIZE 0x4UL 263*4882a593Smuzhiyun #define CC_COMPONENT_ID_2_REG_OFFSET 0x0FF8UL 264*4882a593Smuzhiyun #define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT 0x0UL 265*4882a593Smuzhiyun #define CC_COMPONENT_ID_2_VALUE_BIT_SIZE 0x8UL 266*4882a593Smuzhiyun #define CC_COMPONENT_ID_3_REG_OFFSET 0x0FFCUL 267*4882a593Smuzhiyun #define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT 0x0UL 268*4882a593Smuzhiyun #define CC_COMPONENT_ID_3_VALUE_BIT_SIZE 0x8UL 269*4882a593Smuzhiyun // -------------------------------------- 270*4882a593Smuzhiyun // BLOCK: HOST_SRAM 271*4882a593Smuzhiyun // -------------------------------------- 272*4882a593Smuzhiyun #define CC_SRAM_DATA_REG_OFFSET 0xF00UL 273*4882a593Smuzhiyun #define CC_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL 274*4882a593Smuzhiyun #define CC_SRAM_DATA_VALUE_BIT_SIZE 0x20UL 275*4882a593Smuzhiyun #define CC_SRAM_ADDR_REG_OFFSET 0xF04UL 276*4882a593Smuzhiyun #define CC_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL 277*4882a593Smuzhiyun #define CC_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL 278*4882a593Smuzhiyun #define CC_SRAM_DATA_READY_REG_OFFSET 0xF08UL 279*4882a593Smuzhiyun #define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL 280*4882a593Smuzhiyun #define CC_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun #endif //__CC_HOST_H__ 283