1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* \file cc_aead.h 5*4882a593Smuzhiyun * ARM CryptoCell AEAD Crypto API 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CC_AEAD_H__ 9*4882a593Smuzhiyun #define __CC_AEAD_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/kernel.h> 12*4882a593Smuzhiyun #include <crypto/algapi.h> 13*4882a593Smuzhiyun #include <crypto/ctr.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* mac_cmp - HW writes 8 B but all bytes hold the same value */ 16*4882a593Smuzhiyun #define ICV_CMP_SIZE 8 17*4882a593Smuzhiyun #define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3) 18*4882a593Smuzhiyun #define MAX_MAC_SIZE SHA256_DIGEST_SIZE 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* defines for AES GCM configuration buffer */ 21*4882a593Smuzhiyun #define GCM_BLOCK_LEN_SIZE 8 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define GCM_BLOCK_RFC4_IV_OFFSET 4 24*4882a593Smuzhiyun #define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */ 25*4882a593Smuzhiyun #define GCM_BLOCK_RFC4_NONCE_OFFSET 0 26*4882a593Smuzhiyun #define GCM_BLOCK_RFC4_NONCE_SIZE 4 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Offsets into AES CCM configuration buffer */ 29*4882a593Smuzhiyun #define CCM_B0_OFFSET 0 30*4882a593Smuzhiyun #define CCM_A0_OFFSET 16 31*4882a593Smuzhiyun #define CCM_CTR_COUNT_0_OFFSET 32 32*4882a593Smuzhiyun /* CCM B0 and CTR_COUNT constants. */ 33*4882a593Smuzhiyun #define CCM_BLOCK_NONCE_OFFSET 1 /* Nonce offset inside B0 and CTR_COUNT */ 34*4882a593Smuzhiyun #define CCM_BLOCK_NONCE_SIZE 3 /* Nonce size inside B0 and CTR_COUNT */ 35*4882a593Smuzhiyun #define CCM_BLOCK_IV_OFFSET 4 /* IV offset inside B0 and CTR_COUNT */ 36*4882a593Smuzhiyun #define CCM_BLOCK_IV_SIZE 8 /* IV size inside B0 and CTR_COUNT */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum aead_ccm_header_size { 39*4882a593Smuzhiyun ccm_header_size_null = -1, 40*4882a593Smuzhiyun ccm_header_size_zero = 0, 41*4882a593Smuzhiyun ccm_header_size_2 = 2, 42*4882a593Smuzhiyun ccm_header_size_6 = 6, 43*4882a593Smuzhiyun ccm_header_size_max = S32_MAX 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct aead_req_ctx { 47*4882a593Smuzhiyun /* Allocate cache line although only 4 bytes are needed to 48*4882a593Smuzhiyun * assure next field falls @ cache line 49*4882a593Smuzhiyun * Used for both: digest HW compare and CCM/GCM MAC value 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned; 52*4882a593Smuzhiyun u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun //used in gcm 55*4882a593Smuzhiyun u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned; 56*4882a593Smuzhiyun u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned; 57*4882a593Smuzhiyun u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned; 58*4882a593Smuzhiyun struct { 59*4882a593Smuzhiyun u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned; 60*4882a593Smuzhiyun u8 len_c[GCM_BLOCK_LEN_SIZE]; 61*4882a593Smuzhiyun } gcm_len_block; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; 64*4882a593Smuzhiyun /* HW actual size input */ 65*4882a593Smuzhiyun unsigned int hw_iv_size ____cacheline_aligned; 66*4882a593Smuzhiyun /* used to prevent cache coherence problem */ 67*4882a593Smuzhiyun u8 backup_mac[MAX_MAC_SIZE]; 68*4882a593Smuzhiyun u8 *backup_iv; /* store orig iv */ 69*4882a593Smuzhiyun u32 assoclen; /* size of AAD buffer to authenticate */ 70*4882a593Smuzhiyun dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */ 71*4882a593Smuzhiyun /* buffer for internal ccm configurations */ 72*4882a593Smuzhiyun dma_addr_t ccm_iv0_dma_addr; 73*4882a593Smuzhiyun dma_addr_t icv_dma_addr; /* Phys. address of ICV */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun //used in gcm 76*4882a593Smuzhiyun /* buffer for internal gcm configurations */ 77*4882a593Smuzhiyun dma_addr_t gcm_iv_inc1_dma_addr; 78*4882a593Smuzhiyun /* buffer for internal gcm configurations */ 79*4882a593Smuzhiyun dma_addr_t gcm_iv_inc2_dma_addr; 80*4882a593Smuzhiyun dma_addr_t hkey_dma_addr; /* Phys. address of hkey */ 81*4882a593Smuzhiyun dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun u8 *icv_virt_addr; /* Virt. address of ICV */ 84*4882a593Smuzhiyun struct async_gen_req_ctx gen_ctx; 85*4882a593Smuzhiyun struct cc_mlli assoc; 86*4882a593Smuzhiyun struct cc_mlli src; 87*4882a593Smuzhiyun struct cc_mlli dst; 88*4882a593Smuzhiyun struct scatterlist *src_sgl; 89*4882a593Smuzhiyun struct scatterlist *dst_sgl; 90*4882a593Smuzhiyun unsigned int src_offset; 91*4882a593Smuzhiyun unsigned int dst_offset; 92*4882a593Smuzhiyun enum cc_req_dma_buf_type assoc_buff_type; 93*4882a593Smuzhiyun enum cc_req_dma_buf_type data_buff_type; 94*4882a593Smuzhiyun struct mlli_params mlli_params; 95*4882a593Smuzhiyun unsigned int cryptlen; 96*4882a593Smuzhiyun struct scatterlist ccm_adata_sg; 97*4882a593Smuzhiyun enum aead_ccm_header_size ccm_hdr_size; 98*4882a593Smuzhiyun unsigned int req_authsize; 99*4882a593Smuzhiyun enum drv_cipher_mode cipher_mode; 100*4882a593Smuzhiyun bool is_icv_fragmented; 101*4882a593Smuzhiyun bool is_single_pass; 102*4882a593Smuzhiyun bool plaintext_authenticate_only; //for gcm_rfc4543 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun int cc_aead_alloc(struct cc_drvdata *drvdata); 106*4882a593Smuzhiyun int cc_aead_free(struct cc_drvdata *drvdata); 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /*__CC_AEAD_H__*/ 109