1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Cavium, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __CPTPF_H 7*4882a593Smuzhiyun #define __CPTPF_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "cpt_common.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CSR_DELAY 30 12*4882a593Smuzhiyun #define CPT_MAX_CORE_GROUPS 8 13*4882a593Smuzhiyun #define CPT_MAX_SE_CORES 10 14*4882a593Smuzhiyun #define CPT_MAX_AE_CORES 6 15*4882a593Smuzhiyun #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES) 16*4882a593Smuzhiyun #define CPT_MAX_VF_NUM 16 17*4882a593Smuzhiyun #define CPT_PF_MSIX_VECTORS 3 18*4882a593Smuzhiyun #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a)) 19*4882a593Smuzhiyun #define CPT_UCODE_VERSION_SZ 32 20*4882a593Smuzhiyun struct cpt_device; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct microcode { 23*4882a593Smuzhiyun u8 is_mc_valid; 24*4882a593Smuzhiyun u8 is_ae; 25*4882a593Smuzhiyun u8 group; 26*4882a593Smuzhiyun u8 num_cores; 27*4882a593Smuzhiyun u32 code_size; 28*4882a593Smuzhiyun u64 core_mask; 29*4882a593Smuzhiyun u8 version[CPT_UCODE_VERSION_SZ]; 30*4882a593Smuzhiyun /* Base info */ 31*4882a593Smuzhiyun dma_addr_t phys_base; 32*4882a593Smuzhiyun void *code; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct cpt_vf_info { 36*4882a593Smuzhiyun u8 state; 37*4882a593Smuzhiyun u8 priority; 38*4882a593Smuzhiyun u8 id; 39*4882a593Smuzhiyun u32 qlen; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /** 43*4882a593Smuzhiyun * cpt device structure 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun struct cpt_device { 46*4882a593Smuzhiyun u16 flags; /* Flags to hold device status bits */ 47*4882a593Smuzhiyun u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */ 48*4882a593Smuzhiyun struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun void __iomem *reg_base; /* Register start address */ 51*4882a593Smuzhiyun struct pci_dev *pdev; /* pci device handle */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct microcode mcode[CPT_MAX_CORE_GROUPS]; 54*4882a593Smuzhiyun u8 next_mc_idx; /* next microcode index */ 55*4882a593Smuzhiyun u8 next_group; 56*4882a593Smuzhiyun u8 max_se_cores; 57*4882a593Smuzhiyun u8 max_ae_cores; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx); 61*4882a593Smuzhiyun #endif /* __CPTPF_H */ 62