1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013-2016 Freescale Semiconductor Inc. 4*4882a593Smuzhiyun * Copyright 2017-2018 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DPSECI_CMD_H_ 8*4882a593Smuzhiyun #define _DPSECI_CMD_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* DPSECI Version */ 11*4882a593Smuzhiyun #define DPSECI_VER_MAJOR 5 12*4882a593Smuzhiyun #define DPSECI_VER_MINOR 3 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DPSECI_VER(maj, min) (((maj) << 16) | (min)) 15*4882a593Smuzhiyun #define DPSECI_VERSION DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Command versioning */ 18*4882a593Smuzhiyun #define DPSECI_CMD_BASE_VERSION 1 19*4882a593Smuzhiyun #define DPSECI_CMD_BASE_VERSION_V2 2 20*4882a593Smuzhiyun #define DPSECI_CMD_ID_OFFSET 4 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ 23*4882a593Smuzhiyun DPSECI_CMD_BASE_VERSION) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \ 26*4882a593Smuzhiyun DPSECI_CMD_BASE_VERSION_V2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Command IDs */ 29*4882a593Smuzhiyun #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) 30*4882a593Smuzhiyun #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) 31*4882a593Smuzhiyun #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002) 34*4882a593Smuzhiyun #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003) 35*4882a593Smuzhiyun #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004) 36*4882a593Smuzhiyun #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005) 37*4882a593Smuzhiyun #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) 40*4882a593Smuzhiyun #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) 41*4882a593Smuzhiyun #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197) 42*4882a593Smuzhiyun #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198) 43*4882a593Smuzhiyun #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170) 44*4882a593Smuzhiyun #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Macros for accessing command fields smaller than 1 byte */ 47*4882a593Smuzhiyun #define DPSECI_MASK(field) \ 48*4882a593Smuzhiyun GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \ 49*4882a593Smuzhiyun DPSECI_##field##_SHIFT) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define dpseci_set_field(var, field, val) \ 52*4882a593Smuzhiyun ((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field))) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define dpseci_get_field(var, field) \ 55*4882a593Smuzhiyun (((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct dpseci_cmd_open { 58*4882a593Smuzhiyun __le32 dpseci_id; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define DPSECI_ENABLE_SHIFT 0 62*4882a593Smuzhiyun #define DPSECI_ENABLE_SIZE 1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct dpseci_rsp_is_enabled { 65*4882a593Smuzhiyun u8 is_enabled; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct dpseci_rsp_get_attributes { 69*4882a593Smuzhiyun __le32 id; 70*4882a593Smuzhiyun __le32 pad0; 71*4882a593Smuzhiyun u8 num_tx_queues; 72*4882a593Smuzhiyun u8 num_rx_queues; 73*4882a593Smuzhiyun u8 pad1[6]; 74*4882a593Smuzhiyun __le32 options; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define DPSECI_DEST_TYPE_SHIFT 0 78*4882a593Smuzhiyun #define DPSECI_DEST_TYPE_SIZE 4 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define DPSECI_ORDER_PRESERVATION_SHIFT 0 81*4882a593Smuzhiyun #define DPSECI_ORDER_PRESERVATION_SIZE 1 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct dpseci_cmd_queue { 84*4882a593Smuzhiyun __le32 dest_id; 85*4882a593Smuzhiyun u8 priority; 86*4882a593Smuzhiyun u8 queue; 87*4882a593Smuzhiyun u8 dest_type; 88*4882a593Smuzhiyun u8 pad; 89*4882a593Smuzhiyun __le64 user_ctx; 90*4882a593Smuzhiyun union { 91*4882a593Smuzhiyun __le32 options; 92*4882a593Smuzhiyun __le32 fqid; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun u8 order_preservation_en; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun struct dpseci_rsp_get_tx_queue { 98*4882a593Smuzhiyun __le32 pad; 99*4882a593Smuzhiyun __le32 fqid; 100*4882a593Smuzhiyun u8 priority; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct dpseci_rsp_get_sec_attr { 104*4882a593Smuzhiyun __le16 ip_id; 105*4882a593Smuzhiyun u8 major_rev; 106*4882a593Smuzhiyun u8 minor_rev; 107*4882a593Smuzhiyun u8 era; 108*4882a593Smuzhiyun u8 pad0[3]; 109*4882a593Smuzhiyun u8 deco_num; 110*4882a593Smuzhiyun u8 zuc_auth_acc_num; 111*4882a593Smuzhiyun u8 zuc_enc_acc_num; 112*4882a593Smuzhiyun u8 pad1; 113*4882a593Smuzhiyun u8 snow_f8_acc_num; 114*4882a593Smuzhiyun u8 snow_f9_acc_num; 115*4882a593Smuzhiyun u8 crc_acc_num; 116*4882a593Smuzhiyun u8 pad2; 117*4882a593Smuzhiyun u8 pk_acc_num; 118*4882a593Smuzhiyun u8 kasumi_acc_num; 119*4882a593Smuzhiyun u8 rng_acc_num; 120*4882a593Smuzhiyun u8 pad3; 121*4882a593Smuzhiyun u8 md_acc_num; 122*4882a593Smuzhiyun u8 arc4_acc_num; 123*4882a593Smuzhiyun u8 des_acc_num; 124*4882a593Smuzhiyun u8 aes_acc_num; 125*4882a593Smuzhiyun u8 ccha_acc_num; 126*4882a593Smuzhiyun u8 ptha_acc_num; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun struct dpseci_rsp_get_api_version { 130*4882a593Smuzhiyun __le16 major; 131*4882a593Smuzhiyun __le16 minor; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define DPSECI_CGN_DEST_TYPE_SHIFT 0 135*4882a593Smuzhiyun #define DPSECI_CGN_DEST_TYPE_SIZE 4 136*4882a593Smuzhiyun #define DPSECI_CGN_UNITS_SHIFT 4 137*4882a593Smuzhiyun #define DPSECI_CGN_UNITS_SIZE 2 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct dpseci_cmd_congestion_notification { 140*4882a593Smuzhiyun __le32 dest_id; 141*4882a593Smuzhiyun __le16 notification_mode; 142*4882a593Smuzhiyun u8 priority; 143*4882a593Smuzhiyun u8 options; 144*4882a593Smuzhiyun __le64 message_iova; 145*4882a593Smuzhiyun __le64 message_ctx; 146*4882a593Smuzhiyun __le32 threshold_entry; 147*4882a593Smuzhiyun __le32 threshold_exit; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #endif /* _DPSECI_CMD_H_ */ 151