1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Broadcom 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* 7*4882a593Smuzhiyun * This file contains SPU message definitions specific to SPU-M. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _SPUM_H_ 11*4882a593Smuzhiyun #define _SPUM_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SPU_CRYPTO_OPERATION_GENERIC 0x1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Length of STATUS field in tx and rx packets */ 16*4882a593Smuzhiyun #define SPU_TX_STATUS_LEN 4 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SPU-M error codes */ 19*4882a593Smuzhiyun #define SPU_STATUS_MASK 0x0000FF00 20*4882a593Smuzhiyun #define SPU_STATUS_SUCCESS 0x00000000 21*4882a593Smuzhiyun #define SPU_STATUS_INVALID_ICV 0x00000100 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SPU_STATUS_ERROR_FLAG 0x00020000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Request message. MH + EMH + BDESC + BD header */ 26*4882a593Smuzhiyun #define SPU_REQ_FIXED_LEN 24 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * Max length of a SPU message header. Used to allocate a buffer where 30*4882a593Smuzhiyun * the SPU message header is constructed. Can be used for either a SPU-M 31*4882a593Smuzhiyun * header or a SPU2 header. 32*4882a593Smuzhiyun * For SPU-M, sum of the following: 33*4882a593Smuzhiyun * MH - 4 bytes 34*4882a593Smuzhiyun * EMH - 4 35*4882a593Smuzhiyun * SCTX - 3 + 36*4882a593Smuzhiyun * max auth key len - 64 37*4882a593Smuzhiyun * max cipher key len - 264 (RC4) 38*4882a593Smuzhiyun * max IV len - 16 39*4882a593Smuzhiyun * BDESC - 12 40*4882a593Smuzhiyun * BD header - 4 41*4882a593Smuzhiyun * Total: 371 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * For SPU2, FMD_SIZE (32) plus lengths of hash and cipher keys, 44*4882a593Smuzhiyun * hash and cipher IVs. If SPU2 does not support RC4, then 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define SPU_HEADER_ALLOC_LEN (SPU_REQ_FIXED_LEN + MAX_KEY_SIZE + \ 47*4882a593Smuzhiyun MAX_KEY_SIZE + MAX_IV_SIZE) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Response message header length. Normally MH, EMH, BD header, but when 51*4882a593Smuzhiyun * BD_SUPPRESS is used for hash requests, there is no BD header. 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define SPU_RESP_HDR_LEN 12 54*4882a593Smuzhiyun #define SPU_HASH_RESP_HDR_LEN 8 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Max value that can be represented in the Payload Length field of the BD 58*4882a593Smuzhiyun * header. This is a 16-bit field. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define SPUM_NS2_MAX_PAYLOAD (BIT(16) - 1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * NSP SPU is limited to ~9KB because of FA2 FIFO size limitations; 64*4882a593Smuzhiyun * Set MAX_PAYLOAD to 8k to allow for addition of header, digest, etc. 65*4882a593Smuzhiyun * and stay within limitation. 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define SPUM_NSP_MAX_PAYLOAD 8192 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Buffer Descriptor Header [BDESC]. SPU in big-endian mode. */ 71*4882a593Smuzhiyun struct BDESC_HEADER { 72*4882a593Smuzhiyun u16 offset_mac; /* word 0 [31-16] */ 73*4882a593Smuzhiyun u16 length_mac; /* word 0 [15-0] */ 74*4882a593Smuzhiyun u16 offset_crypto; /* word 1 [31-16] */ 75*4882a593Smuzhiyun u16 length_crypto; /* word 1 [15-0] */ 76*4882a593Smuzhiyun u16 offset_icv; /* word 2 [31-16] */ 77*4882a593Smuzhiyun u16 offset_iv; /* word 2 [15-0] */ 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Buffer Data Header [BD]. SPU in big-endian mode. */ 81*4882a593Smuzhiyun struct BD_HEADER { 82*4882a593Smuzhiyun u16 size; 83*4882a593Smuzhiyun u16 prev_length; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Command Context Header. SPU-M in big endian mode. */ 87*4882a593Smuzhiyun struct MHEADER { 88*4882a593Smuzhiyun u8 flags; /* [31:24] */ 89*4882a593Smuzhiyun u8 op_code; /* [23:16] */ 90*4882a593Smuzhiyun u16 reserved; /* [15:0] */ 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* MH header flags bits */ 94*4882a593Smuzhiyun #define MH_SUPDT_PRES BIT(0) 95*4882a593Smuzhiyun #define MH_HASH_PRES BIT(2) 96*4882a593Smuzhiyun #define MH_BD_PRES BIT(3) 97*4882a593Smuzhiyun #define MH_MFM_PRES BIT(4) 98*4882a593Smuzhiyun #define MH_BDESC_PRES BIT(5) 99*4882a593Smuzhiyun #define MH_SCTX_PRES BIT(7) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* SCTX word 0 bit offsets and fields masks */ 102*4882a593Smuzhiyun #define SCTX_SIZE 0x000000FF 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* SCTX word 1 bit shifts and field masks */ 105*4882a593Smuzhiyun #define UPDT_OFST 0x000000FF /* offset of SCTX updateable fld */ 106*4882a593Smuzhiyun #define HASH_TYPE 0x00000300 /* hash alg operation type */ 107*4882a593Smuzhiyun #define HASH_TYPE_SHIFT 8 108*4882a593Smuzhiyun #define HASH_MODE 0x00001C00 /* one of spu2_hash_mode */ 109*4882a593Smuzhiyun #define HASH_MODE_SHIFT 10 110*4882a593Smuzhiyun #define HASH_ALG 0x0000E000 /* hash algorithm */ 111*4882a593Smuzhiyun #define HASH_ALG_SHIFT 13 112*4882a593Smuzhiyun #define CIPHER_TYPE 0x00030000 /* encryption operation type */ 113*4882a593Smuzhiyun #define CIPHER_TYPE_SHIFT 16 114*4882a593Smuzhiyun #define CIPHER_MODE 0x001C0000 /* encryption mode */ 115*4882a593Smuzhiyun #define CIPHER_MODE_SHIFT 18 116*4882a593Smuzhiyun #define CIPHER_ALG 0x00E00000 /* encryption algo */ 117*4882a593Smuzhiyun #define CIPHER_ALG_SHIFT 21 118*4882a593Smuzhiyun #define ICV_IS_512 BIT(27) 119*4882a593Smuzhiyun #define ICV_IS_512_SHIFT 27 120*4882a593Smuzhiyun #define CIPHER_ORDER BIT(30) 121*4882a593Smuzhiyun #define CIPHER_ORDER_SHIFT 30 122*4882a593Smuzhiyun #define CIPHER_INBOUND BIT(31) 123*4882a593Smuzhiyun #define CIPHER_INBOUND_SHIFT 31 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* SCTX word 2 bit shifts and field masks */ 126*4882a593Smuzhiyun #define EXP_IV_SIZE 0x7 127*4882a593Smuzhiyun #define IV_OFFSET BIT(3) 128*4882a593Smuzhiyun #define IV_OFFSET_SHIFT 3 129*4882a593Smuzhiyun #define GEN_IV BIT(5) 130*4882a593Smuzhiyun #define GEN_IV_SHIFT 5 131*4882a593Smuzhiyun #define EXPLICIT_IV BIT(6) 132*4882a593Smuzhiyun #define EXPLICIT_IV_SHIFT 6 133*4882a593Smuzhiyun #define SCTX_IV BIT(7) 134*4882a593Smuzhiyun #define SCTX_IV_SHIFT 7 135*4882a593Smuzhiyun #define ICV_SIZE 0x0F00 136*4882a593Smuzhiyun #define ICV_SIZE_SHIFT 8 137*4882a593Smuzhiyun #define CHECK_ICV BIT(12) 138*4882a593Smuzhiyun #define CHECK_ICV_SHIFT 12 139*4882a593Smuzhiyun #define INSERT_ICV BIT(13) 140*4882a593Smuzhiyun #define INSERT_ICV_SHIFT 13 141*4882a593Smuzhiyun #define BD_SUPPRESS BIT(19) 142*4882a593Smuzhiyun #define BD_SUPPRESS_SHIFT 19 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Generic Mode Security Context Structure [SCTX] */ 145*4882a593Smuzhiyun struct SCTX { 146*4882a593Smuzhiyun /* word 0: protocol flags */ 147*4882a593Smuzhiyun u32 proto_flags; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* word 1: cipher flags */ 150*4882a593Smuzhiyun u32 cipher_flags; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* word 2: Extended cipher flags */ 153*4882a593Smuzhiyun u32 ecf; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun struct SPUHEADER { 158*4882a593Smuzhiyun struct MHEADER mh; 159*4882a593Smuzhiyun u32 emh; 160*4882a593Smuzhiyun struct SCTX sa; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #endif /* _SPUM_H_ */ 164