1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ATMEL_AES_REGS_H__ 3*4882a593Smuzhiyun #define __ATMEL_AES_REGS_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define AES_CR 0x00 6*4882a593Smuzhiyun #define AES_CR_START (1 << 0) 7*4882a593Smuzhiyun #define AES_CR_SWRST (1 << 8) 8*4882a593Smuzhiyun #define AES_CR_LOADSEED (1 << 16) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AES_MR 0x04 11*4882a593Smuzhiyun #define AES_MR_CYPHER_DEC (0 << 0) 12*4882a593Smuzhiyun #define AES_MR_CYPHER_ENC (1 << 0) 13*4882a593Smuzhiyun #define AES_MR_GTAGEN (1 << 1) 14*4882a593Smuzhiyun #define AES_MR_DUALBUFF (1 << 3) 15*4882a593Smuzhiyun #define AES_MR_PROCDLY_MASK (0xF << 4) 16*4882a593Smuzhiyun #define AES_MR_PROCDLY_OFFSET 4 17*4882a593Smuzhiyun #define AES_MR_SMOD_MASK (0x3 << 8) 18*4882a593Smuzhiyun #define AES_MR_SMOD_MANUAL (0x0 << 8) 19*4882a593Smuzhiyun #define AES_MR_SMOD_AUTO (0x1 << 8) 20*4882a593Smuzhiyun #define AES_MR_SMOD_IDATAR0 (0x2 << 8) 21*4882a593Smuzhiyun #define AES_MR_KEYSIZE_MASK (0x3 << 10) 22*4882a593Smuzhiyun #define AES_MR_KEYSIZE_128 (0x0 << 10) 23*4882a593Smuzhiyun #define AES_MR_KEYSIZE_192 (0x1 << 10) 24*4882a593Smuzhiyun #define AES_MR_KEYSIZE_256 (0x2 << 10) 25*4882a593Smuzhiyun #define AES_MR_OPMOD_MASK (0x7 << 12) 26*4882a593Smuzhiyun #define AES_MR_OPMOD_ECB (0x0 << 12) 27*4882a593Smuzhiyun #define AES_MR_OPMOD_CBC (0x1 << 12) 28*4882a593Smuzhiyun #define AES_MR_OPMOD_OFB (0x2 << 12) 29*4882a593Smuzhiyun #define AES_MR_OPMOD_CFB (0x3 << 12) 30*4882a593Smuzhiyun #define AES_MR_OPMOD_CTR (0x4 << 12) 31*4882a593Smuzhiyun #define AES_MR_OPMOD_GCM (0x5 << 12) 32*4882a593Smuzhiyun #define AES_MR_OPMOD_XTS (0x6 << 12) 33*4882a593Smuzhiyun #define AES_MR_LOD (0x1 << 15) 34*4882a593Smuzhiyun #define AES_MR_CFBS_MASK (0x7 << 16) 35*4882a593Smuzhiyun #define AES_MR_CFBS_128b (0x0 << 16) 36*4882a593Smuzhiyun #define AES_MR_CFBS_64b (0x1 << 16) 37*4882a593Smuzhiyun #define AES_MR_CFBS_32b (0x2 << 16) 38*4882a593Smuzhiyun #define AES_MR_CFBS_16b (0x3 << 16) 39*4882a593Smuzhiyun #define AES_MR_CFBS_8b (0x4 << 16) 40*4882a593Smuzhiyun #define AES_MR_CKEY_MASK (0xF << 20) 41*4882a593Smuzhiyun #define AES_MR_CKEY_OFFSET 20 42*4882a593Smuzhiyun #define AES_MR_CMTYP_MASK (0x1F << 24) 43*4882a593Smuzhiyun #define AES_MR_CMTYP_OFFSET 24 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AES_IER 0x10 46*4882a593Smuzhiyun #define AES_IDR 0x14 47*4882a593Smuzhiyun #define AES_IMR 0x18 48*4882a593Smuzhiyun #define AES_ISR 0x1C 49*4882a593Smuzhiyun #define AES_INT_DATARDY (1 << 0) 50*4882a593Smuzhiyun #define AES_INT_URAD (1 << 8) 51*4882a593Smuzhiyun #define AES_INT_TAGRDY (1 << 16) 52*4882a593Smuzhiyun #define AES_ISR_URAT_MASK (0xF << 12) 53*4882a593Smuzhiyun #define AES_ISR_URAT_IDR_WR_PROC (0x0 << 12) 54*4882a593Smuzhiyun #define AES_ISR_URAT_ODR_RD_PROC (0x1 << 12) 55*4882a593Smuzhiyun #define AES_ISR_URAT_MR_WR_PROC (0x2 << 12) 56*4882a593Smuzhiyun #define AES_ISR_URAT_ODR_RD_SUBK (0x3 << 12) 57*4882a593Smuzhiyun #define AES_ISR_URAT_MR_WR_SUBK (0x4 << 12) 58*4882a593Smuzhiyun #define AES_ISR_URAT_WOR_RD (0x5 << 12) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define AES_KEYWR(x) (0x20 + ((x) * 0x04)) 61*4882a593Smuzhiyun #define AES_IDATAR(x) (0x40 + ((x) * 0x04)) 62*4882a593Smuzhiyun #define AES_ODATAR(x) (0x50 + ((x) * 0x04)) 63*4882a593Smuzhiyun #define AES_IVR(x) (0x60 + ((x) * 0x04)) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define AES_AADLENR 0x70 66*4882a593Smuzhiyun #define AES_CLENR 0x74 67*4882a593Smuzhiyun #define AES_GHASHR(x) (0x78 + ((x) * 0x04)) 68*4882a593Smuzhiyun #define AES_TAGR(x) (0x88 + ((x) * 0x04)) 69*4882a593Smuzhiyun #define AES_CTRR 0x98 70*4882a593Smuzhiyun #define AES_GCMHR(x) (0x9c + ((x) * 0x04)) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define AES_EMR 0xb0 73*4882a593Smuzhiyun #define AES_EMR_APEN BIT(0) /* Auto Padding Enable */ 74*4882a593Smuzhiyun #define AES_EMR_APM BIT(1) /* Auto Padding Mode */ 75*4882a593Smuzhiyun #define AES_EMR_APM_IPSEC 0x0 76*4882a593Smuzhiyun #define AES_EMR_APM_SSL BIT(1) 77*4882a593Smuzhiyun #define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */ 78*4882a593Smuzhiyun #define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */ 79*4882a593Smuzhiyun #define AES_EMR_PADLEN_MASK (0xFu << 8) 80*4882a593Smuzhiyun #define AES_EMR_PADLEN_OFFSET 8 81*4882a593Smuzhiyun #define AES_EMR_PADLEN(padlen) (((padlen) << AES_EMR_PADLEN_OFFSET) &\ 82*4882a593Smuzhiyun AES_EMR_PADLEN_MASK) 83*4882a593Smuzhiyun #define AES_EMR_NHEAD_MASK (0xFu << 16) 84*4882a593Smuzhiyun #define AES_EMR_NHEAD_OFFSET 16 85*4882a593Smuzhiyun #define AES_EMR_NHEAD(nhead) (((nhead) << AES_EMR_NHEAD_OFFSET) &\ 86*4882a593Smuzhiyun AES_EMR_NHEAD_MASK) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define AES_TWR(x) (0xc0 + ((x) * 0x04)) 89*4882a593Smuzhiyun #define AES_ALPHAR(x) (0xd0 + ((x) * 0x04)) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define AES_HW_VERSION 0xFC 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* __ATMEL_AES_REGS_H__ */ 94