1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012-2013 Xilinx
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * CPU idle support for Xilinx Zynq
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * based on arch/arm/mach-at91/cpuidle.c
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10*4882a593Smuzhiyun * to implement two idle states -
11*4882a593Smuzhiyun * #1 wait-for-interrupt
12*4882a593Smuzhiyun * #2 wait-for-interrupt and RAM self refresh
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Maintainer: Michal Simek <michal.simek@xilinx.com>
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/cpuidle.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <asm/cpuidle.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define ZYNQ_MAX_STATES 2
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Actual code that puts the SoC in different idle states */
zynq_enter_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)25*4882a593Smuzhiyun static int zynq_enter_idle(struct cpuidle_device *dev,
26*4882a593Smuzhiyun struct cpuidle_driver *drv, int index)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun /* Add code for DDR self refresh start */
29*4882a593Smuzhiyun cpu_do_idle();
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return index;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static struct cpuidle_driver zynq_idle_driver = {
35*4882a593Smuzhiyun .name = "zynq_idle",
36*4882a593Smuzhiyun .owner = THIS_MODULE,
37*4882a593Smuzhiyun .states = {
38*4882a593Smuzhiyun ARM_CPUIDLE_WFI_STATE,
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun .enter = zynq_enter_idle,
41*4882a593Smuzhiyun .exit_latency = 10,
42*4882a593Smuzhiyun .target_residency = 10000,
43*4882a593Smuzhiyun .name = "RAM_SR",
44*4882a593Smuzhiyun .desc = "WFI and RAM Self Refresh",
45*4882a593Smuzhiyun },
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun .safe_state_index = 0,
48*4882a593Smuzhiyun .state_count = ZYNQ_MAX_STATES,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Initialize CPU idle by registering the idle states */
zynq_cpuidle_probe(struct platform_device * pdev)52*4882a593Smuzhiyun static int zynq_cpuidle_probe(struct platform_device *pdev)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun pr_info("Xilinx Zynq CpuIdle Driver started\n");
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return cpuidle_register(&zynq_idle_driver, NULL);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct platform_driver zynq_cpuidle_driver = {
60*4882a593Smuzhiyun .driver = {
61*4882a593Smuzhiyun .name = "cpuidle-zynq",
62*4882a593Smuzhiyun },
63*4882a593Smuzhiyun .probe = zynq_cpuidle_probe,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun builtin_platform_driver(zynq_cpuidle_driver);
66