1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2010 Google, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author:
6*4882a593Smuzhiyun * Colin Cross <ccross@google.com>
7*4882a593Smuzhiyun * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bits.h>
11*4882a593Smuzhiyun #include <linux/cpu.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/pm_opp.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <soc/tegra/common.h>
21*4882a593Smuzhiyun #include <soc/tegra/fuse.h>
22*4882a593Smuzhiyun
cpu0_node_has_opp_v2_prop(void)23*4882a593Smuzhiyun static bool cpu0_node_has_opp_v2_prop(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct device_node *np = of_cpu_device_node_get(0);
26*4882a593Smuzhiyun bool ret = false;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (of_get_property(np, "operating-points-v2", NULL))
29*4882a593Smuzhiyun ret = true;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun of_node_put(np);
32*4882a593Smuzhiyun return ret;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
tegra20_cpufreq_probe(struct platform_device * pdev)35*4882a593Smuzhiyun static int tegra20_cpufreq_probe(struct platform_device *pdev)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct platform_device *cpufreq_dt;
38*4882a593Smuzhiyun struct opp_table *opp_table;
39*4882a593Smuzhiyun struct device *cpu_dev;
40*4882a593Smuzhiyun u32 versions[2];
41*4882a593Smuzhiyun int err;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (!cpu0_node_has_opp_v2_prop()) {
44*4882a593Smuzhiyun dev_err(&pdev->dev, "operating points not found\n");
45*4882a593Smuzhiyun dev_err(&pdev->dev, "please update your device tree\n");
46*4882a593Smuzhiyun return -ENODEV;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (of_machine_is_compatible("nvidia,tegra20")) {
50*4882a593Smuzhiyun versions[0] = BIT(tegra_sku_info.cpu_process_id);
51*4882a593Smuzhiyun versions[1] = BIT(tegra_sku_info.soc_speedo_id);
52*4882a593Smuzhiyun } else {
53*4882a593Smuzhiyun versions[0] = BIT(tegra_sku_info.cpu_process_id);
54*4882a593Smuzhiyun versions[1] = BIT(tegra_sku_info.cpu_speedo_id);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n",
58*4882a593Smuzhiyun versions[0], versions[1]);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun cpu_dev = get_cpu_device(0);
61*4882a593Smuzhiyun if (WARN_ON(!cpu_dev))
62*4882a593Smuzhiyun return -ENODEV;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2);
65*4882a593Smuzhiyun err = PTR_ERR_OR_ZERO(opp_table);
66*4882a593Smuzhiyun if (err) {
67*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to set supported hw: %d\n", err);
68*4882a593Smuzhiyun return err;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
72*4882a593Smuzhiyun err = PTR_ERR_OR_ZERO(cpufreq_dt);
73*4882a593Smuzhiyun if (err) {
74*4882a593Smuzhiyun dev_err(&pdev->dev,
75*4882a593Smuzhiyun "failed to create cpufreq-dt device: %d\n", err);
76*4882a593Smuzhiyun goto err_put_supported_hw;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun platform_set_drvdata(pdev, cpufreq_dt);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun err_put_supported_hw:
84*4882a593Smuzhiyun dev_pm_opp_put_supported_hw(opp_table);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return err;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
tegra20_cpufreq_remove(struct platform_device * pdev)89*4882a593Smuzhiyun static int tegra20_cpufreq_remove(struct platform_device *pdev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct platform_device *cpufreq_dt;
92*4882a593Smuzhiyun struct opp_table *opp_table;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun cpufreq_dt = platform_get_drvdata(pdev);
95*4882a593Smuzhiyun platform_device_unregister(cpufreq_dt);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0));
98*4882a593Smuzhiyun dev_pm_opp_put_supported_hw(opp_table);
99*4882a593Smuzhiyun dev_pm_opp_put_opp_table(opp_table);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct platform_driver tegra20_cpufreq_driver = {
105*4882a593Smuzhiyun .probe = tegra20_cpufreq_probe,
106*4882a593Smuzhiyun .remove = tegra20_cpufreq_remove,
107*4882a593Smuzhiyun .driver = {
108*4882a593Smuzhiyun .name = "tegra20-cpufreq",
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun module_platform_driver(tegra20_cpufreq_driver);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun MODULE_ALIAS("platform:tegra20-cpufreq");
114*4882a593Smuzhiyun MODULE_AUTHOR("Colin Cross <ccross@android.com>");
115*4882a593Smuzhiyun MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
116*4882a593Smuzhiyun MODULE_LICENSE("GPL");
117