1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __ROCKCHIP_CPUFREQ_H 6*4882a593Smuzhiyun #define __ROCKCHIP_CPUFREQ_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_ARM_ROCKCHIP_CPUFREQ) 9*4882a593Smuzhiyun int rockchip_cpufreq_adjust_power_scale(struct device *dev); 10*4882a593Smuzhiyun int rockchip_cpufreq_opp_set_rate(struct device *dev, unsigned long target_freq); 11*4882a593Smuzhiyun #else rockchip_cpufreq_adjust_power_scale(struct device * dev)12*4882a593Smuzhiyunstatic inline int rockchip_cpufreq_adjust_power_scale(struct device *dev) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun return -EOPNOTSUPP; 15*4882a593Smuzhiyun } 16*4882a593Smuzhiyun rockchip_cpufreq_opp_set_rate(struct device * dev,unsigned long target_freq)17*4882a593Smuzhiyunstatic inline int rockchip_cpufreq_opp_set_rate(struct device *dev, 18*4882a593Smuzhiyun unsigned long target_freq) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun return -EOPNOTSUPP; 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun #endif /* CONFIG_ARM_ROCKCHIP_CPUFREQ */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif 25