xref: /OK3568_Linux_fs/kernel/drivers/cpufreq/pxa2xx-cpufreq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (C) 2002,2003 Intrinsyc Software
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * History:
6*4882a593Smuzhiyun  *   31-Jul-2002 : Initial version [FB]
7*4882a593Smuzhiyun  *   29-Jan-2003 : added PXA255 support [FB]
8*4882a593Smuzhiyun  *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Note:
11*4882a593Smuzhiyun  *   This driver may change the memory bus clock rate, but will not do any
12*4882a593Smuzhiyun  *   platform specific access timing changes... for example if you have flash
13*4882a593Smuzhiyun  *   memory connected to CS0, you will need to register a platform specific
14*4882a593Smuzhiyun  *   notifier which will adjust the memory access strobes to maintain a
15*4882a593Smuzhiyun  *   minimum strobe width.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/sched.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/cpufreq.h>
25*4882a593Smuzhiyun #include <linux/err.h>
26*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
27*4882a593Smuzhiyun #include <linux/io.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include <mach/pxa2xx-regs.h>
30*4882a593Smuzhiyun #include <mach/smemc.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #ifdef DEBUG
33*4882a593Smuzhiyun static unsigned int freq_debug;
34*4882a593Smuzhiyun module_param(freq_debug, uint, 0);
35*4882a593Smuzhiyun MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
36*4882a593Smuzhiyun #else
37*4882a593Smuzhiyun #define freq_debug  0
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static struct regulator *vcc_core;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun static unsigned int pxa27x_maxfreq;
43*4882a593Smuzhiyun module_param(pxa27x_maxfreq, uint, 0);
44*4882a593Smuzhiyun MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
45*4882a593Smuzhiyun 		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct pxa_cpufreq_data {
48*4882a593Smuzhiyun 	struct clk *clk_core;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun static struct pxa_cpufreq_data  pxa_cpufreq_data;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct pxa_freqs {
53*4882a593Smuzhiyun 	unsigned int khz;
54*4882a593Smuzhiyun 	int vmin;
55*4882a593Smuzhiyun 	int vmax;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun  * PXA255 definitions
60*4882a593Smuzhiyun  */
61*4882a593Smuzhiyun static const struct pxa_freqs pxa255_run_freqs[] =
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	/* CPU   MEMBUS		   run  turbo PXbus SDRAM */
64*4882a593Smuzhiyun 	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
65*4882a593Smuzhiyun 	{132700, -1, -1},	/* 133,  133,   66,   66  */
66*4882a593Smuzhiyun 	{199100, -1, -1},	/* 199,  199,   99,   99  */
67*4882a593Smuzhiyun 	{265400, -1, -1},	/* 265,  265,  133,   66  */
68*4882a593Smuzhiyun 	{331800, -1, -1},	/* 331,  331,  166,   83  */
69*4882a593Smuzhiyun 	{398100, -1, -1},	/* 398,  398,  196,   99  */
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
73*4882a593Smuzhiyun static const struct pxa_freqs pxa255_turbo_freqs[] =
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	/* CPU			   run  turbo PXbus SDRAM */
76*4882a593Smuzhiyun 	{ 99500, -1, -1},	/*  99,   99,   50,   50  */
77*4882a593Smuzhiyun 	{199100, -1, -1},	/*  99,  199,   50,   99  */
78*4882a593Smuzhiyun 	{298500, -1, -1},	/*  99,  287,   50,   99  */
79*4882a593Smuzhiyun 	{298600, -1, -1},	/* 199,  287,   99,   99  */
80*4882a593Smuzhiyun 	{398100, -1, -1},	/* 199,  398,   99,   99  */
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
84*4882a593Smuzhiyun #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct cpufreq_frequency_table
87*4882a593Smuzhiyun 	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
88*4882a593Smuzhiyun static struct cpufreq_frequency_table
89*4882a593Smuzhiyun 	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static unsigned int pxa255_turbo_table;
92*4882a593Smuzhiyun module_param(pxa255_turbo_table, uint, 0);
93*4882a593Smuzhiyun MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun static struct pxa_freqs pxa27x_freqs[] = {
96*4882a593Smuzhiyun 	{104000,  900000, 1705000 },
97*4882a593Smuzhiyun 	{156000, 1000000, 1705000 },
98*4882a593Smuzhiyun 	{208000, 1180000, 1705000 },
99*4882a593Smuzhiyun 	{312000, 1250000, 1705000 },
100*4882a593Smuzhiyun 	{416000, 1350000, 1705000 },
101*4882a593Smuzhiyun 	{520000, 1450000, 1705000 },
102*4882a593Smuzhiyun 	{624000, 1550000, 1705000 }
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
106*4882a593Smuzhiyun static struct cpufreq_frequency_table
107*4882a593Smuzhiyun 	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun extern unsigned get_clk_frequency_khz(int info);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #ifdef CONFIG_REGULATOR
112*4882a593Smuzhiyun 
pxa_cpufreq_change_voltage(const struct pxa_freqs * pxa_freq)113*4882a593Smuzhiyun static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	int ret = 0;
116*4882a593Smuzhiyun 	int vmin, vmax;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (!cpu_is_pxa27x())
119*4882a593Smuzhiyun 		return 0;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	vmin = pxa_freq->vmin;
122*4882a593Smuzhiyun 	vmax = pxa_freq->vmax;
123*4882a593Smuzhiyun 	if ((vmin == -1) || (vmax == -1))
124*4882a593Smuzhiyun 		return 0;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	ret = regulator_set_voltage(vcc_core, vmin, vmax);
127*4882a593Smuzhiyun 	if (ret)
128*4882a593Smuzhiyun 		pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
129*4882a593Smuzhiyun 	return ret;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
pxa_cpufreq_init_voltages(void)132*4882a593Smuzhiyun static void pxa_cpufreq_init_voltages(void)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	vcc_core = regulator_get(NULL, "vcc_core");
135*4882a593Smuzhiyun 	if (IS_ERR(vcc_core)) {
136*4882a593Smuzhiyun 		pr_info("Didn't find vcc_core regulator\n");
137*4882a593Smuzhiyun 		vcc_core = NULL;
138*4882a593Smuzhiyun 	} else {
139*4882a593Smuzhiyun 		pr_info("Found vcc_core regulator\n");
140*4882a593Smuzhiyun 	}
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun #else
pxa_cpufreq_change_voltage(const struct pxa_freqs * pxa_freq)143*4882a593Smuzhiyun static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
pxa_cpufreq_init_voltages(void)148*4882a593Smuzhiyun static void pxa_cpufreq_init_voltages(void) { }
149*4882a593Smuzhiyun #endif
150*4882a593Smuzhiyun 
find_freq_tables(struct cpufreq_frequency_table ** freq_table,const struct pxa_freqs ** pxa_freqs)151*4882a593Smuzhiyun static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
152*4882a593Smuzhiyun 			     const struct pxa_freqs **pxa_freqs)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	if (cpu_is_pxa25x()) {
155*4882a593Smuzhiyun 		if (!pxa255_turbo_table) {
156*4882a593Smuzhiyun 			*pxa_freqs = pxa255_run_freqs;
157*4882a593Smuzhiyun 			*freq_table = pxa255_run_freq_table;
158*4882a593Smuzhiyun 		} else {
159*4882a593Smuzhiyun 			*pxa_freqs = pxa255_turbo_freqs;
160*4882a593Smuzhiyun 			*freq_table = pxa255_turbo_freq_table;
161*4882a593Smuzhiyun 		}
162*4882a593Smuzhiyun 	} else if (cpu_is_pxa27x()) {
163*4882a593Smuzhiyun 		*pxa_freqs = pxa27x_freqs;
164*4882a593Smuzhiyun 		*freq_table = pxa27x_freq_table;
165*4882a593Smuzhiyun 	} else {
166*4882a593Smuzhiyun 		BUG();
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
pxa27x_guess_max_freq(void)170*4882a593Smuzhiyun static void pxa27x_guess_max_freq(void)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	if (!pxa27x_maxfreq) {
173*4882a593Smuzhiyun 		pxa27x_maxfreq = 416000;
174*4882a593Smuzhiyun 		pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
175*4882a593Smuzhiyun 			pxa27x_maxfreq);
176*4882a593Smuzhiyun 	} else {
177*4882a593Smuzhiyun 		pxa27x_maxfreq *= 1000;
178*4882a593Smuzhiyun 	}
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
pxa_cpufreq_get(unsigned int cpu)181*4882a593Smuzhiyun static unsigned int pxa_cpufreq_get(unsigned int cpu)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return (unsigned int) clk_get_rate(data->clk_core) / 1000;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
pxa_set_target(struct cpufreq_policy * policy,unsigned int idx)188*4882a593Smuzhiyun static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct cpufreq_frequency_table *pxa_freqs_table;
191*4882a593Smuzhiyun 	const struct pxa_freqs *pxa_freq_settings;
192*4882a593Smuzhiyun 	struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
193*4882a593Smuzhiyun 	unsigned int new_freq_cpu;
194*4882a593Smuzhiyun 	int ret = 0;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* Get the current policy */
197*4882a593Smuzhiyun 	find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	new_freq_cpu = pxa_freq_settings[idx].khz;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	if (freq_debug)
202*4882a593Smuzhiyun 		pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
203*4882a593Smuzhiyun 			 policy->cur / 1000,  new_freq_cpu / 1000);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	if (vcc_core && new_freq_cpu > policy->cur) {
206*4882a593Smuzhiyun 		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
207*4882a593Smuzhiyun 		if (ret)
208*4882a593Smuzhiyun 			return ret;
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	clk_set_rate(data->clk_core, new_freq_cpu * 1000);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	/*
214*4882a593Smuzhiyun 	 * Even if voltage setting fails, we don't report it, as the frequency
215*4882a593Smuzhiyun 	 * change succeeded. The voltage reduction is not a critical failure,
216*4882a593Smuzhiyun 	 * only power savings will suffer from this.
217*4882a593Smuzhiyun 	 *
218*4882a593Smuzhiyun 	 * Note: if the voltage change fails, and a return value is returned, a
219*4882a593Smuzhiyun 	 * bug is triggered (seems a deadlock). Should anybody find out where,
220*4882a593Smuzhiyun 	 * the "return 0" should become a "return ret".
221*4882a593Smuzhiyun 	 */
222*4882a593Smuzhiyun 	if (vcc_core && new_freq_cpu < policy->cur)
223*4882a593Smuzhiyun 		ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
pxa_cpufreq_init(struct cpufreq_policy * policy)228*4882a593Smuzhiyun static int pxa_cpufreq_init(struct cpufreq_policy *policy)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	int i;
231*4882a593Smuzhiyun 	unsigned int freq;
232*4882a593Smuzhiyun 	struct cpufreq_frequency_table *pxa255_freq_table;
233*4882a593Smuzhiyun 	const struct pxa_freqs *pxa255_freqs;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* try to guess pxa27x cpu */
236*4882a593Smuzhiyun 	if (cpu_is_pxa27x())
237*4882a593Smuzhiyun 		pxa27x_guess_max_freq();
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	pxa_cpufreq_init_voltages();
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	/* set default policy and cpuinfo */
242*4882a593Smuzhiyun 	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* Generate pxa25x the run cpufreq_frequency_table struct */
245*4882a593Smuzhiyun 	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
246*4882a593Smuzhiyun 		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
247*4882a593Smuzhiyun 		pxa255_run_freq_table[i].driver_data = i;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
252*4882a593Smuzhiyun 	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
253*4882a593Smuzhiyun 		pxa255_turbo_freq_table[i].frequency =
254*4882a593Smuzhiyun 			pxa255_turbo_freqs[i].khz;
255*4882a593Smuzhiyun 		pxa255_turbo_freq_table[i].driver_data = i;
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun 	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	pxa255_turbo_table = !!pxa255_turbo_table;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	/* Generate the pxa27x cpufreq_frequency_table struct */
262*4882a593Smuzhiyun 	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
263*4882a593Smuzhiyun 		freq = pxa27x_freqs[i].khz;
264*4882a593Smuzhiyun 		if (freq > pxa27x_maxfreq)
265*4882a593Smuzhiyun 			break;
266*4882a593Smuzhiyun 		pxa27x_freq_table[i].frequency = freq;
267*4882a593Smuzhiyun 		pxa27x_freq_table[i].driver_data = i;
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 	pxa27x_freq_table[i].driver_data = i;
270*4882a593Smuzhiyun 	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/*
273*4882a593Smuzhiyun 	 * Set the policy's minimum and maximum frequencies from the tables
274*4882a593Smuzhiyun 	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
275*4882a593Smuzhiyun 	 */
276*4882a593Smuzhiyun 	if (cpu_is_pxa25x()) {
277*4882a593Smuzhiyun 		find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
278*4882a593Smuzhiyun 		pr_info("using %s frequency table\n",
279*4882a593Smuzhiyun 			pxa255_turbo_table ? "turbo" : "run");
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 		policy->freq_table = pxa255_freq_table;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 	else if (cpu_is_pxa27x()) {
284*4882a593Smuzhiyun 		policy->freq_table = pxa27x_freq_table;
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	pr_info("frequency change support initialized\n");
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static struct cpufreq_driver pxa_cpufreq_driver = {
293*4882a593Smuzhiyun 	.flags	= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
294*4882a593Smuzhiyun 	.verify	= cpufreq_generic_frequency_table_verify,
295*4882a593Smuzhiyun 	.target_index = pxa_set_target,
296*4882a593Smuzhiyun 	.init	= pxa_cpufreq_init,
297*4882a593Smuzhiyun 	.get	= pxa_cpufreq_get,
298*4882a593Smuzhiyun 	.name	= "PXA2xx",
299*4882a593Smuzhiyun 	.driver_data = &pxa_cpufreq_data,
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun 
pxa_cpu_init(void)302*4882a593Smuzhiyun static int __init pxa_cpu_init(void)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	int ret = -ENODEV;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
307*4882a593Smuzhiyun 	if (IS_ERR(pxa_cpufreq_data.clk_core))
308*4882a593Smuzhiyun 		return PTR_ERR(pxa_cpufreq_data.clk_core);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (cpu_is_pxa25x() || cpu_is_pxa27x())
311*4882a593Smuzhiyun 		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
312*4882a593Smuzhiyun 	return ret;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun 
pxa_cpu_exit(void)315*4882a593Smuzhiyun static void __exit pxa_cpu_exit(void)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun 	cpufreq_unregister_driver(&pxa_cpufreq_driver);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun MODULE_AUTHOR("Intrinsyc Software Inc.");
322*4882a593Smuzhiyun MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
323*4882a593Smuzhiyun MODULE_LICENSE("GPL");
324*4882a593Smuzhiyun module_init(pxa_cpu_init);
325*4882a593Smuzhiyun module_exit(pxa_cpu_exit);
326