1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) 2003 Dave Jones. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * AMD-specific information 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun union msr_fidvidctl { 9*4882a593Smuzhiyun struct { 10*4882a593Smuzhiyun unsigned FID:5, // 4:0 11*4882a593Smuzhiyun reserved1:3, // 7:5 12*4882a593Smuzhiyun VID:5, // 12:8 13*4882a593Smuzhiyun reserved2:3, // 15:13 14*4882a593Smuzhiyun FIDC:1, // 16 15*4882a593Smuzhiyun VIDC:1, // 17 16*4882a593Smuzhiyun reserved3:2, // 19:18 17*4882a593Smuzhiyun FIDCHGRATIO:1, // 20 18*4882a593Smuzhiyun reserved4:11, // 31-21 19*4882a593Smuzhiyun SGTC:20, // 32:51 20*4882a593Smuzhiyun reserved5:12; // 63:52 21*4882a593Smuzhiyun } bits; 22*4882a593Smuzhiyun unsigned long long val; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun union msr_fidvidstatus { 26*4882a593Smuzhiyun struct { 27*4882a593Smuzhiyun unsigned CFID:5, // 4:0 28*4882a593Smuzhiyun reserved1:3, // 7:5 29*4882a593Smuzhiyun SFID:5, // 12:8 30*4882a593Smuzhiyun reserved2:3, // 15:13 31*4882a593Smuzhiyun MFID:5, // 20:16 32*4882a593Smuzhiyun reserved3:11, // 31:21 33*4882a593Smuzhiyun CVID:5, // 36:32 34*4882a593Smuzhiyun reserved4:3, // 39:37 35*4882a593Smuzhiyun SVID:5, // 44:40 36*4882a593Smuzhiyun reserved5:3, // 47:45 37*4882a593Smuzhiyun MVID:5, // 52:48 38*4882a593Smuzhiyun reserved6:11; // 63:53 39*4882a593Smuzhiyun } bits; 40*4882a593Smuzhiyun unsigned long long val; 41*4882a593Smuzhiyun }; 42