1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * CPUFreq support for Armada 370/XP platforms.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012-2016 Marvell
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Yehuda Yitschak <yehuday@marvell.com>
7*4882a593Smuzhiyun * Gregory Clement <gregory.clement@free-electrons.com>
8*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
11*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
12*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define pr_fmt(fmt) "mvebu-pmsu: " fmt
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <linux/cpu.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/of_address.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/pm_opp.h>
24*4882a593Smuzhiyun #include <linux/resource.h>
25*4882a593Smuzhiyun
armada_xp_pmsu_cpufreq_init(void)26*4882a593Smuzhiyun static int __init armada_xp_pmsu_cpufreq_init(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun struct device_node *np;
29*4882a593Smuzhiyun struct resource res;
30*4882a593Smuzhiyun int ret, cpu;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if (!of_machine_is_compatible("marvell,armadaxp"))
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * In order to have proper cpufreq handling, we need to ensure
37*4882a593Smuzhiyun * that the Device Tree description of the CPU clock includes
38*4882a593Smuzhiyun * the definition of the PMU DFS registers. If not, we do not
39*4882a593Smuzhiyun * register the clock notifier and the cpufreq driver. This
40*4882a593Smuzhiyun * piece of code is only for compatibility with old Device
41*4882a593Smuzhiyun * Trees.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock");
44*4882a593Smuzhiyun if (!np)
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun ret = of_address_to_resource(np, 1, &res);
48*4882a593Smuzhiyun if (ret) {
49*4882a593Smuzhiyun pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n");
50*4882a593Smuzhiyun of_node_put(np);
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun of_node_put(np);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * For each CPU, this loop registers the operating points
58*4882a593Smuzhiyun * supported (which are the nominal CPU frequency and half of
59*4882a593Smuzhiyun * it), and registers the clock notifier that will take care
60*4882a593Smuzhiyun * of doing the PMSU part of a frequency transition.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun for_each_possible_cpu(cpu) {
63*4882a593Smuzhiyun struct device *cpu_dev;
64*4882a593Smuzhiyun struct clk *clk;
65*4882a593Smuzhiyun int ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun cpu_dev = get_cpu_device(cpu);
68*4882a593Smuzhiyun if (!cpu_dev) {
69*4882a593Smuzhiyun pr_err("Cannot get CPU %d\n", cpu);
70*4882a593Smuzhiyun continue;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun clk = clk_get(cpu_dev, NULL);
74*4882a593Smuzhiyun if (IS_ERR(clk)) {
75*4882a593Smuzhiyun pr_err("Cannot get clock for CPU %d\n", cpu);
76*4882a593Smuzhiyun return PTR_ERR(clk);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
80*4882a593Smuzhiyun if (ret) {
81*4882a593Smuzhiyun clk_put(clk);
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
86*4882a593Smuzhiyun if (ret) {
87*4882a593Smuzhiyun dev_pm_opp_remove(cpu_dev, clk_get_rate(clk));
88*4882a593Smuzhiyun clk_put(clk);
89*4882a593Smuzhiyun dev_err(cpu_dev, "Failed to register OPPs\n");
90*4882a593Smuzhiyun return ret;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ret = dev_pm_opp_set_sharing_cpus(cpu_dev,
94*4882a593Smuzhiyun cpumask_of(cpu_dev->id));
95*4882a593Smuzhiyun if (ret)
96*4882a593Smuzhiyun dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
97*4882a593Smuzhiyun __func__, ret);
98*4882a593Smuzhiyun clk_put(clk);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun device_initcall(armada_xp_pmsu_cpufreq_init);
105