1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * kirkwood_freq.c: cpufreq driver for the Marvell kirkwood
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/cpufreq.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <asm/proc-fns.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define CPU_SW_INT_BLK BIT(28)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static struct priv
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct clk *cpu_clk;
22*4882a593Smuzhiyun struct clk *ddr_clk;
23*4882a593Smuzhiyun struct clk *powersave_clk;
24*4882a593Smuzhiyun struct device *dev;
25*4882a593Smuzhiyun void __iomem *base;
26*4882a593Smuzhiyun } priv;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define STATE_CPU_FREQ 0x01
29*4882a593Smuzhiyun #define STATE_DDR_FREQ 0x02
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Kirkwood can swap the clock to the CPU between two clocks:
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * - cpu clk
35*4882a593Smuzhiyun * - ddr clk
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * The frequencies are set at runtime before registering this table.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun static struct cpufreq_frequency_table kirkwood_freq_table[] = {
40*4882a593Smuzhiyun {0, STATE_CPU_FREQ, 0}, /* CPU uses cpuclk */
41*4882a593Smuzhiyun {0, STATE_DDR_FREQ, 0}, /* CPU uses ddrclk */
42*4882a593Smuzhiyun {0, 0, CPUFREQ_TABLE_END},
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
kirkwood_cpufreq_get_cpu_frequency(unsigned int cpu)45*4882a593Smuzhiyun static unsigned int kirkwood_cpufreq_get_cpu_frequency(unsigned int cpu)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun return clk_get_rate(priv.powersave_clk) / 1000;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
kirkwood_cpufreq_target(struct cpufreq_policy * policy,unsigned int index)50*4882a593Smuzhiyun static int kirkwood_cpufreq_target(struct cpufreq_policy *policy,
51*4882a593Smuzhiyun unsigned int index)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun unsigned int state = kirkwood_freq_table[index].driver_data;
54*4882a593Smuzhiyun unsigned long reg;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun local_irq_disable();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Disable interrupts to the CPU */
59*4882a593Smuzhiyun reg = readl_relaxed(priv.base);
60*4882a593Smuzhiyun reg |= CPU_SW_INT_BLK;
61*4882a593Smuzhiyun writel_relaxed(reg, priv.base);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun switch (state) {
64*4882a593Smuzhiyun case STATE_CPU_FREQ:
65*4882a593Smuzhiyun clk_set_parent(priv.powersave_clk, priv.cpu_clk);
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case STATE_DDR_FREQ:
68*4882a593Smuzhiyun clk_set_parent(priv.powersave_clk, priv.ddr_clk);
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Wait-for-Interrupt, while the hardware changes frequency */
73*4882a593Smuzhiyun cpu_do_idle();
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Enable interrupts to the CPU */
76*4882a593Smuzhiyun reg = readl_relaxed(priv.base);
77*4882a593Smuzhiyun reg &= ~CPU_SW_INT_BLK;
78*4882a593Smuzhiyun writel_relaxed(reg, priv.base);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun local_irq_enable();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Module init and exit code */
kirkwood_cpufreq_cpu_init(struct cpufreq_policy * policy)86*4882a593Smuzhiyun static int kirkwood_cpufreq_cpu_init(struct cpufreq_policy *policy)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun cpufreq_generic_init(policy, kirkwood_freq_table, 5000);
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static struct cpufreq_driver kirkwood_cpufreq_driver = {
93*4882a593Smuzhiyun .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
94*4882a593Smuzhiyun .get = kirkwood_cpufreq_get_cpu_frequency,
95*4882a593Smuzhiyun .verify = cpufreq_generic_frequency_table_verify,
96*4882a593Smuzhiyun .target_index = kirkwood_cpufreq_target,
97*4882a593Smuzhiyun .init = kirkwood_cpufreq_cpu_init,
98*4882a593Smuzhiyun .name = "kirkwood-cpufreq",
99*4882a593Smuzhiyun .attr = cpufreq_generic_attr,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
kirkwood_cpufreq_probe(struct platform_device * pdev)102*4882a593Smuzhiyun static int kirkwood_cpufreq_probe(struct platform_device *pdev)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct device_node *np;
105*4882a593Smuzhiyun int err;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun priv.dev = &pdev->dev;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun priv.base = devm_platform_ioremap_resource(pdev, 0);
110*4882a593Smuzhiyun if (IS_ERR(priv.base))
111*4882a593Smuzhiyun return PTR_ERR(priv.base);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun np = of_cpu_device_node_get(0);
114*4882a593Smuzhiyun if (!np) {
115*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get cpu device node\n");
116*4882a593Smuzhiyun return -ENODEV;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun priv.cpu_clk = of_clk_get_by_name(np, "cpu_clk");
120*4882a593Smuzhiyun if (IS_ERR(priv.cpu_clk)) {
121*4882a593Smuzhiyun dev_err(priv.dev, "Unable to get cpuclk\n");
122*4882a593Smuzhiyun err = PTR_ERR(priv.cpu_clk);
123*4882a593Smuzhiyun goto out_node;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun err = clk_prepare_enable(priv.cpu_clk);
127*4882a593Smuzhiyun if (err) {
128*4882a593Smuzhiyun dev_err(priv.dev, "Unable to prepare cpuclk\n");
129*4882a593Smuzhiyun goto out_node;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun priv.ddr_clk = of_clk_get_by_name(np, "ddrclk");
135*4882a593Smuzhiyun if (IS_ERR(priv.ddr_clk)) {
136*4882a593Smuzhiyun dev_err(priv.dev, "Unable to get ddrclk\n");
137*4882a593Smuzhiyun err = PTR_ERR(priv.ddr_clk);
138*4882a593Smuzhiyun goto out_cpu;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun err = clk_prepare_enable(priv.ddr_clk);
142*4882a593Smuzhiyun if (err) {
143*4882a593Smuzhiyun dev_err(priv.dev, "Unable to prepare ddrclk\n");
144*4882a593Smuzhiyun goto out_cpu;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun kirkwood_freq_table[1].frequency = clk_get_rate(priv.ddr_clk) / 1000;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun priv.powersave_clk = of_clk_get_by_name(np, "powersave");
149*4882a593Smuzhiyun if (IS_ERR(priv.powersave_clk)) {
150*4882a593Smuzhiyun dev_err(priv.dev, "Unable to get powersave\n");
151*4882a593Smuzhiyun err = PTR_ERR(priv.powersave_clk);
152*4882a593Smuzhiyun goto out_ddr;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun err = clk_prepare_enable(priv.powersave_clk);
155*4882a593Smuzhiyun if (err) {
156*4882a593Smuzhiyun dev_err(priv.dev, "Unable to prepare powersave clk\n");
157*4882a593Smuzhiyun goto out_ddr;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun err = cpufreq_register_driver(&kirkwood_cpufreq_driver);
161*4882a593Smuzhiyun if (err) {
162*4882a593Smuzhiyun dev_err(priv.dev, "Failed to register cpufreq driver\n");
163*4882a593Smuzhiyun goto out_powersave;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun of_node_put(np);
167*4882a593Smuzhiyun return 0;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun out_powersave:
170*4882a593Smuzhiyun clk_disable_unprepare(priv.powersave_clk);
171*4882a593Smuzhiyun out_ddr:
172*4882a593Smuzhiyun clk_disable_unprepare(priv.ddr_clk);
173*4882a593Smuzhiyun out_cpu:
174*4882a593Smuzhiyun clk_disable_unprepare(priv.cpu_clk);
175*4882a593Smuzhiyun out_node:
176*4882a593Smuzhiyun of_node_put(np);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return err;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
kirkwood_cpufreq_remove(struct platform_device * pdev)181*4882a593Smuzhiyun static int kirkwood_cpufreq_remove(struct platform_device *pdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun cpufreq_unregister_driver(&kirkwood_cpufreq_driver);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun clk_disable_unprepare(priv.powersave_clk);
186*4882a593Smuzhiyun clk_disable_unprepare(priv.ddr_clk);
187*4882a593Smuzhiyun clk_disable_unprepare(priv.cpu_clk);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static struct platform_driver kirkwood_cpufreq_platform_driver = {
193*4882a593Smuzhiyun .probe = kirkwood_cpufreq_probe,
194*4882a593Smuzhiyun .remove = kirkwood_cpufreq_remove,
195*4882a593Smuzhiyun .driver = {
196*4882a593Smuzhiyun .name = "kirkwood-cpufreq",
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun module_platform_driver(kirkwood_cpufreq_platform_driver);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
203*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch");
204*4882a593Smuzhiyun MODULE_DESCRIPTION("cpufreq driver for Marvell's kirkwood CPU");
205*4882a593Smuzhiyun MODULE_ALIAS("platform:kirkwood-cpufreq");
206