xref: /OK3568_Linux_fs/kernel/drivers/clocksource/timer-vt8500.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  arch/arm/mach-vt8500/timer.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6*4882a593Smuzhiyun  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun  * This file is copied and modified from the original timer.c provided by
11*4882a593Smuzhiyun  * Alexey Charkov. Minor changes have been made for Device Tree Support.
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/clocksource.h>
18*4882a593Smuzhiyun #include <linux/clockchips.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <linux/of_address.h>
23*4882a593Smuzhiyun #include <linux/of_irq.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define VT8500_TIMER_OFFSET	0x0100
26*4882a593Smuzhiyun #define VT8500_TIMER_HZ		3000000
27*4882a593Smuzhiyun #define TIMER_MATCH_VAL		0x0000
28*4882a593Smuzhiyun #define TIMER_COUNT_VAL		0x0010
29*4882a593Smuzhiyun #define TIMER_STATUS_VAL	0x0014
30*4882a593Smuzhiyun #define TIMER_IER_VAL		0x001c		/* interrupt enable */
31*4882a593Smuzhiyun #define TIMER_CTRL_VAL		0x0020
32*4882a593Smuzhiyun #define TIMER_AS_VAL		0x0024		/* access status */
33*4882a593Smuzhiyun #define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
34*4882a593Smuzhiyun #define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
35*4882a593Smuzhiyun #define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define MIN_OSCR_DELTA		16
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun static void __iomem *regbase;
42*4882a593Smuzhiyun 
vt8500_timer_read(struct clocksource * cs)43*4882a593Smuzhiyun static u64 vt8500_timer_read(struct clocksource *cs)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	int loops = msecs_to_loops(10);
46*4882a593Smuzhiyun 	writel(3, regbase + TIMER_CTRL_VAL);
47*4882a593Smuzhiyun 	while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
48*4882a593Smuzhiyun 						&& --loops)
49*4882a593Smuzhiyun 		cpu_relax();
50*4882a593Smuzhiyun 	return readl(regbase + TIMER_COUNT_VAL);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static struct clocksource clocksource = {
54*4882a593Smuzhiyun 	.name           = "vt8500_timer",
55*4882a593Smuzhiyun 	.rating         = 200,
56*4882a593Smuzhiyun 	.read           = vt8500_timer_read,
57*4882a593Smuzhiyun 	.mask           = CLOCKSOURCE_MASK(32),
58*4882a593Smuzhiyun 	.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
vt8500_timer_set_next_event(unsigned long cycles,struct clock_event_device * evt)61*4882a593Smuzhiyun static int vt8500_timer_set_next_event(unsigned long cycles,
62*4882a593Smuzhiyun 				    struct clock_event_device *evt)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	int loops = msecs_to_loops(10);
65*4882a593Smuzhiyun 	u64 alarm = clocksource.read(&clocksource) + cycles;
66*4882a593Smuzhiyun 	while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
67*4882a593Smuzhiyun 						&& --loops)
68*4882a593Smuzhiyun 		cpu_relax();
69*4882a593Smuzhiyun 	writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA)
72*4882a593Smuzhiyun 		return -ETIME;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	writel(1, regbase + TIMER_IER_VAL);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
vt8500_shutdown(struct clock_event_device * evt)79*4882a593Smuzhiyun static int vt8500_shutdown(struct clock_event_device *evt)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL);
82*4882a593Smuzhiyun 	writel(0, regbase + TIMER_IER_VAL);
83*4882a593Smuzhiyun 	return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static struct clock_event_device clockevent = {
87*4882a593Smuzhiyun 	.name			= "vt8500_timer",
88*4882a593Smuzhiyun 	.features		= CLOCK_EVT_FEAT_ONESHOT,
89*4882a593Smuzhiyun 	.rating			= 200,
90*4882a593Smuzhiyun 	.set_next_event		= vt8500_timer_set_next_event,
91*4882a593Smuzhiyun 	.set_state_shutdown	= vt8500_shutdown,
92*4882a593Smuzhiyun 	.set_state_oneshot	= vt8500_shutdown,
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
vt8500_timer_interrupt(int irq,void * dev_id)95*4882a593Smuzhiyun static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct clock_event_device *evt = dev_id;
98*4882a593Smuzhiyun 	writel(0xf, regbase + TIMER_STATUS_VAL);
99*4882a593Smuzhiyun 	evt->event_handler(evt);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return IRQ_HANDLED;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
vt8500_timer_init(struct device_node * np)104*4882a593Smuzhiyun static int __init vt8500_timer_init(struct device_node *np)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	int timer_irq, ret;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	regbase = of_iomap(np, 0);
109*4882a593Smuzhiyun 	if (!regbase) {
110*4882a593Smuzhiyun 		pr_err("%s: Missing iobase description in Device Tree\n",
111*4882a593Smuzhiyun 								__func__);
112*4882a593Smuzhiyun 		return -ENXIO;
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	timer_irq = irq_of_parse_and_map(np, 0);
116*4882a593Smuzhiyun 	if (!timer_irq) {
117*4882a593Smuzhiyun 		pr_err("%s: Missing irq description in Device Tree\n",
118*4882a593Smuzhiyun 								__func__);
119*4882a593Smuzhiyun 		return -EINVAL;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	writel(1, regbase + TIMER_CTRL_VAL);
123*4882a593Smuzhiyun 	writel(0xf, regbase + TIMER_STATUS_VAL);
124*4882a593Smuzhiyun 	writel(~0, regbase + TIMER_MATCH_VAL);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
127*4882a593Smuzhiyun 	if (ret) {
128*4882a593Smuzhiyun 		pr_err("%s: clocksource_register failed for %s\n",
129*4882a593Smuzhiyun 		       __func__, clocksource.name);
130*4882a593Smuzhiyun 		return ret;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	clockevent.cpumask = cpumask_of(0);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	ret = request_irq(timer_irq, vt8500_timer_interrupt,
136*4882a593Smuzhiyun 			  IRQF_TIMER | IRQF_IRQPOLL, "vt8500_timer",
137*4882a593Smuzhiyun 			  &clockevent);
138*4882a593Smuzhiyun 	if (ret) {
139*4882a593Smuzhiyun 		pr_err("%s: setup_irq failed for %s\n", __func__,
140*4882a593Smuzhiyun 							clockevent.name);
141*4882a593Smuzhiyun 		return ret;
142*4882a593Smuzhiyun 	}
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
145*4882a593Smuzhiyun 					MIN_OSCR_DELTA * 2, 0xf0000000);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun TIMER_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
151