1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) Maxime Coquelin 2015
4*4882a593Smuzhiyun * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Inspired by time-efm32.c from Uwe Kleine-Koenig
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/clocksource.h>
11*4882a593Smuzhiyun #include <linux/clockchips.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_address.h>
17*4882a593Smuzhiyun #include <linux/of_irq.h>
18*4882a593Smuzhiyun #include <linux/clk.h>
19*4882a593Smuzhiyun #include <linux/reset.h>
20*4882a593Smuzhiyun #include <linux/sched_clock.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "timer-of.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define TIM_CR1 0x00
26*4882a593Smuzhiyun #define TIM_DIER 0x0c
27*4882a593Smuzhiyun #define TIM_SR 0x10
28*4882a593Smuzhiyun #define TIM_EGR 0x14
29*4882a593Smuzhiyun #define TIM_CNT 0x24
30*4882a593Smuzhiyun #define TIM_PSC 0x28
31*4882a593Smuzhiyun #define TIM_ARR 0x2c
32*4882a593Smuzhiyun #define TIM_CCR1 0x34
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define TIM_CR1_CEN BIT(0)
35*4882a593Smuzhiyun #define TIM_CR1_UDIS BIT(1)
36*4882a593Smuzhiyun #define TIM_CR1_OPM BIT(3)
37*4882a593Smuzhiyun #define TIM_CR1_ARPE BIT(7)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define TIM_DIER_UIE BIT(0)
40*4882a593Smuzhiyun #define TIM_DIER_CC1IE BIT(1)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define TIM_SR_UIF BIT(0)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define TIM_EGR_UG BIT(0)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define TIM_PSC_MAX USHRT_MAX
47*4882a593Smuzhiyun #define TIM_PSC_CLKRATE 10000
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct stm32_timer_private {
50*4882a593Smuzhiyun int bits;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun * stm32_timer_of_bits_set - set accessor helper
55*4882a593Smuzhiyun * @to: a timer_of structure pointer
56*4882a593Smuzhiyun * @bits: the number of bits (16 or 32)
57*4882a593Smuzhiyun *
58*4882a593Smuzhiyun * Accessor helper to set the number of bits in the timer-of private
59*4882a593Smuzhiyun * structure.
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun */
stm32_timer_of_bits_set(struct timer_of * to,int bits)62*4882a593Smuzhiyun static void stm32_timer_of_bits_set(struct timer_of *to, int bits)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct stm32_timer_private *pd = to->private_data;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun pd->bits = bits;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /**
70*4882a593Smuzhiyun * stm32_timer_of_bits_get - get accessor helper
71*4882a593Smuzhiyun * @to: a timer_of structure pointer
72*4882a593Smuzhiyun *
73*4882a593Smuzhiyun * Accessor helper to get the number of bits in the timer-of private
74*4882a593Smuzhiyun * structure.
75*4882a593Smuzhiyun *
76*4882a593Smuzhiyun * Returns an integer corresponding to the number of bits.
77*4882a593Smuzhiyun */
stm32_timer_of_bits_get(struct timer_of * to)78*4882a593Smuzhiyun static int stm32_timer_of_bits_get(struct timer_of *to)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct stm32_timer_private *pd = to->private_data;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return pd->bits;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static void __iomem *stm32_timer_cnt __read_mostly;
86*4882a593Smuzhiyun
stm32_read_sched_clock(void)87*4882a593Smuzhiyun static u64 notrace stm32_read_sched_clock(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return readl_relaxed(stm32_timer_cnt);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static struct delay_timer stm32_timer_delay;
93*4882a593Smuzhiyun
stm32_read_delay(void)94*4882a593Smuzhiyun static unsigned long stm32_read_delay(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun return readl_relaxed(stm32_timer_cnt);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
stm32_clock_event_disable(struct timer_of * to)99*4882a593Smuzhiyun static void stm32_clock_event_disable(struct timer_of *to)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun writel_relaxed(0, timer_of_base(to) + TIM_DIER);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /**
105*4882a593Smuzhiyun * stm32_timer_start - Start the counter without event
106*4882a593Smuzhiyun * @to: a timer_of structure pointer
107*4882a593Smuzhiyun *
108*4882a593Smuzhiyun * Start the timer in order to have the counter reset and start
109*4882a593Smuzhiyun * incrementing but disable interrupt event when there is a counter
110*4882a593Smuzhiyun * overflow. By default, the counter direction is used as upcounter.
111*4882a593Smuzhiyun */
stm32_timer_start(struct timer_of * to)112*4882a593Smuzhiyun static void stm32_timer_start(struct timer_of *to)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
stm32_clock_event_shutdown(struct clock_event_device * clkevt)117*4882a593Smuzhiyun static int stm32_clock_event_shutdown(struct clock_event_device *clkevt)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct timer_of *to = to_timer_of(clkevt);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun stm32_clock_event_disable(to);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
stm32_clock_event_set_next_event(unsigned long evt,struct clock_event_device * clkevt)126*4882a593Smuzhiyun static int stm32_clock_event_set_next_event(unsigned long evt,
127*4882a593Smuzhiyun struct clock_event_device *clkevt)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun struct timer_of *to = to_timer_of(clkevt);
130*4882a593Smuzhiyun unsigned long now, next;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt;
133*4882a593Smuzhiyun writel_relaxed(next, timer_of_base(to) + TIM_CCR1);
134*4882a593Smuzhiyun now = readl_relaxed(timer_of_base(to) + TIM_CNT);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if ((next - now) > evt)
137*4882a593Smuzhiyun return -ETIME;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
stm32_clock_event_set_periodic(struct clock_event_device * clkevt)144*4882a593Smuzhiyun static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct timer_of *to = to_timer_of(clkevt);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun stm32_timer_start(to);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return stm32_clock_event_set_next_event(timer_of_period(to), clkevt);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
stm32_clock_event_set_oneshot(struct clock_event_device * clkevt)153*4882a593Smuzhiyun static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct timer_of *to = to_timer_of(clkevt);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun stm32_timer_start(to);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
stm32_clock_event_handler(int irq,void * dev_id)162*4882a593Smuzhiyun static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
165*4882a593Smuzhiyun struct timer_of *to = to_timer_of(clkevt);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun writel_relaxed(0, timer_of_base(to) + TIM_SR);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (clockevent_state_periodic(clkevt))
170*4882a593Smuzhiyun stm32_clock_event_set_periodic(clkevt);
171*4882a593Smuzhiyun else
172*4882a593Smuzhiyun stm32_clock_event_shutdown(clkevt);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun clkevt->event_handler(clkevt);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return IRQ_HANDLED;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /**
180*4882a593Smuzhiyun * stm32_timer_width - Sort out the timer width (32/16)
181*4882a593Smuzhiyun * @to: a pointer to a timer-of structure
182*4882a593Smuzhiyun *
183*4882a593Smuzhiyun * Write the 32-bit max value and read/return the result. If the timer
184*4882a593Smuzhiyun * is 32 bits wide, the result will be UINT_MAX, otherwise it will
185*4882a593Smuzhiyun * be truncated by the 16-bit register to USHRT_MAX.
186*4882a593Smuzhiyun *
187*4882a593Smuzhiyun */
stm32_timer_set_width(struct timer_of * to)188*4882a593Smuzhiyun static void __init stm32_timer_set_width(struct timer_of *to)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun u32 width;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun width = readl_relaxed(timer_of_base(to) + TIM_ARR);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun stm32_timer_of_bits_set(to, width == UINT_MAX ? 32 : 16);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /**
200*4882a593Smuzhiyun * stm32_timer_set_prescaler - Compute and set the prescaler register
201*4882a593Smuzhiyun * @to: a pointer to a timer-of structure
202*4882a593Smuzhiyun *
203*4882a593Smuzhiyun * Depending on the timer width, compute the prescaler to always
204*4882a593Smuzhiyun * target a 10MHz timer rate for 16 bits. 32-bit timers are
205*4882a593Smuzhiyun * considered precise and long enough to not use the prescaler.
206*4882a593Smuzhiyun */
stm32_timer_set_prescaler(struct timer_of * to)207*4882a593Smuzhiyun static void __init stm32_timer_set_prescaler(struct timer_of *to)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun int prescaler = 1;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (stm32_timer_of_bits_get(to) != 32) {
212*4882a593Smuzhiyun prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to),
213*4882a593Smuzhiyun TIM_PSC_CLKRATE);
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun * The prescaler register is an u16, the variable
216*4882a593Smuzhiyun * can't be greater than TIM_PSC_MAX, let's cap it in
217*4882a593Smuzhiyun * this case.
218*4882a593Smuzhiyun */
219*4882a593Smuzhiyun prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
223*4882a593Smuzhiyun writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
224*4882a593Smuzhiyun writel_relaxed(0, timer_of_base(to) + TIM_SR);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Adjust rate and period given the prescaler value */
227*4882a593Smuzhiyun to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler);
228*4882a593Smuzhiyun to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
stm32_clocksource_init(struct timer_of * to)231*4882a593Smuzhiyun static int __init stm32_clocksource_init(struct timer_of *to)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun u32 bits = stm32_timer_of_bits_get(to);
234*4882a593Smuzhiyun const char *name = to->np->full_name;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /*
237*4882a593Smuzhiyun * This driver allows to register several timers and relies on
238*4882a593Smuzhiyun * the generic time framework to select the right one.
239*4882a593Smuzhiyun * However, nothing allows to do the same for the
240*4882a593Smuzhiyun * sched_clock. We are not interested in a sched_clock for the
241*4882a593Smuzhiyun * 16-bit timers but only for the 32-bit one, so if no 32-bit
242*4882a593Smuzhiyun * timer is registered yet, we select this 32-bit timer as a
243*4882a593Smuzhiyun * sched_clock.
244*4882a593Smuzhiyun */
245*4882a593Smuzhiyun if (bits == 32 && !stm32_timer_cnt) {
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /*
248*4882a593Smuzhiyun * Start immediately the counter as we will be using
249*4882a593Smuzhiyun * it right after.
250*4882a593Smuzhiyun */
251*4882a593Smuzhiyun stm32_timer_start(to);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun stm32_timer_cnt = timer_of_base(to) + TIM_CNT;
254*4882a593Smuzhiyun sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to));
255*4882a593Smuzhiyun pr_info("%s: STM32 sched_clock registered\n", name);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun stm32_timer_delay.read_current_timer = stm32_read_delay;
258*4882a593Smuzhiyun stm32_timer_delay.freq = timer_of_rate(to);
259*4882a593Smuzhiyun register_current_timer_delay(&stm32_timer_delay);
260*4882a593Smuzhiyun pr_info("%s: STM32 delay timer registered\n", name);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name,
264*4882a593Smuzhiyun timer_of_rate(to), bits == 32 ? 250 : 100,
265*4882a593Smuzhiyun bits, clocksource_mmio_readl_up);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
stm32_clockevent_init(struct timer_of * to)268*4882a593Smuzhiyun static void __init stm32_clockevent_init(struct timer_of *to)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun u32 bits = stm32_timer_of_bits_get(to);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun to->clkevt.name = to->np->full_name;
273*4882a593Smuzhiyun to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
274*4882a593Smuzhiyun to->clkevt.set_state_shutdown = stm32_clock_event_shutdown;
275*4882a593Smuzhiyun to->clkevt.set_state_periodic = stm32_clock_event_set_periodic;
276*4882a593Smuzhiyun to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot;
277*4882a593Smuzhiyun to->clkevt.tick_resume = stm32_clock_event_shutdown;
278*4882a593Smuzhiyun to->clkevt.set_next_event = stm32_clock_event_set_next_event;
279*4882a593Smuzhiyun to->clkevt.rating = bits == 32 ? 250 : 100;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 0x1,
282*4882a593Smuzhiyun (1 << bits) - 1);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
285*4882a593Smuzhiyun to->np, bits);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
stm32_timer_init(struct device_node * node)288*4882a593Smuzhiyun static int __init stm32_timer_init(struct device_node *node)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct reset_control *rstc;
291*4882a593Smuzhiyun struct timer_of *to;
292*4882a593Smuzhiyun int ret;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun to = kzalloc(sizeof(*to), GFP_KERNEL);
295*4882a593Smuzhiyun if (!to)
296*4882a593Smuzhiyun return -ENOMEM;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
299*4882a593Smuzhiyun to->of_irq.handler = stm32_clock_event_handler;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun ret = timer_of_init(node, to);
302*4882a593Smuzhiyun if (ret)
303*4882a593Smuzhiyun goto err;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun to->private_data = kzalloc(sizeof(struct stm32_timer_private),
306*4882a593Smuzhiyun GFP_KERNEL);
307*4882a593Smuzhiyun if (!to->private_data) {
308*4882a593Smuzhiyun ret = -ENOMEM;
309*4882a593Smuzhiyun goto deinit;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun rstc = of_reset_control_get(node, NULL);
313*4882a593Smuzhiyun if (!IS_ERR(rstc)) {
314*4882a593Smuzhiyun reset_control_assert(rstc);
315*4882a593Smuzhiyun reset_control_deassert(rstc);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun stm32_timer_set_width(to);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun stm32_timer_set_prescaler(to);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun ret = stm32_clocksource_init(to);
323*4882a593Smuzhiyun if (ret)
324*4882a593Smuzhiyun goto deinit;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun stm32_clockevent_init(to);
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun deinit:
330*4882a593Smuzhiyun timer_of_cleanup(to);
331*4882a593Smuzhiyun err:
332*4882a593Smuzhiyun kfree(to);
333*4882a593Smuzhiyun return ret;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);
337