1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ARM timer implementation, found in Integrator, Versatile and Realview 4*4882a593Smuzhiyun * platforms. Not all platforms support all registers and bits in these 5*4882a593Smuzhiyun * registers, so we mark them with A for Integrator AP, C for Integrator 6*4882a593Smuzhiyun * CP, V for Versatile and R for Realview. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview 9*4882a593Smuzhiyun * can have 16-bit or 32-bit selectable via a bit in the control register. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Every SP804 contains two identical timers. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define NR_TIMERS 2 14*4882a593Smuzhiyun #define TIMER_1_BASE 0x00 15*4882a593Smuzhiyun #define TIMER_2_BASE 0x20 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define TIMER_LOAD 0x00 /* ACVR rw */ 18*4882a593Smuzhiyun #define TIMER_VALUE 0x04 /* ACVR ro */ 19*4882a593Smuzhiyun #define TIMER_CTRL 0x08 /* ACVR rw */ 20*4882a593Smuzhiyun #define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */ 21*4882a593Smuzhiyun #define TIMER_CTRL_32BIT (1 << 1) /* CVR */ 22*4882a593Smuzhiyun #define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */ 23*4882a593Smuzhiyun #define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */ 24*4882a593Smuzhiyun #define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */ 25*4882a593Smuzhiyun #define TIMER_CTRL_IE (1 << 5) /* VR */ 26*4882a593Smuzhiyun #define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */ 27*4882a593Smuzhiyun #define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define TIMER_INTCLR 0x0c /* ACVR wo */ 30*4882a593Smuzhiyun #define TIMER_RIS 0x10 /* CVR ro */ 31*4882a593Smuzhiyun #define TIMER_MIS 0x14 /* CVR ro */ 32*4882a593Smuzhiyun #define TIMER_BGLOAD 0x18 /* CVR rw */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct sp804_timer { 35*4882a593Smuzhiyun int load; 36*4882a593Smuzhiyun int load_h; 37*4882a593Smuzhiyun int value; 38*4882a593Smuzhiyun int value_h; 39*4882a593Smuzhiyun int ctrl; 40*4882a593Smuzhiyun int intclr; 41*4882a593Smuzhiyun int ris; 42*4882a593Smuzhiyun int mis; 43*4882a593Smuzhiyun int bgload; 44*4882a593Smuzhiyun int bgload_h; 45*4882a593Smuzhiyun int timer_base[NR_TIMERS]; 46*4882a593Smuzhiyun int width; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct sp804_clkevt { 50*4882a593Smuzhiyun void __iomem *base; 51*4882a593Smuzhiyun void __iomem *load; 52*4882a593Smuzhiyun void __iomem *load_h; 53*4882a593Smuzhiyun void __iomem *value; 54*4882a593Smuzhiyun void __iomem *value_h; 55*4882a593Smuzhiyun void __iomem *ctrl; 56*4882a593Smuzhiyun void __iomem *intclr; 57*4882a593Smuzhiyun void __iomem *ris; 58*4882a593Smuzhiyun void __iomem *mis; 59*4882a593Smuzhiyun void __iomem *bgload; 60*4882a593Smuzhiyun void __iomem *bgload_h; 61*4882a593Smuzhiyun unsigned long reload; 62*4882a593Smuzhiyun int width; 63*4882a593Smuzhiyun }; 64