xref: /OK3568_Linux_fs/kernel/drivers/clocksource/timer-milbeaut.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2018 Socionext Inc.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/irq.h>
9*4882a593Smuzhiyun #include <linux/irqreturn.h>
10*4882a593Smuzhiyun #include <linux/sched_clock.h>
11*4882a593Smuzhiyun #include "timer-of.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define MLB_TMR_TMCSR_OFS	0x0
14*4882a593Smuzhiyun #define MLB_TMR_TMR_OFS		0x4
15*4882a593Smuzhiyun #define MLB_TMR_TMRLR1_OFS	0x8
16*4882a593Smuzhiyun #define MLB_TMR_TMRLR2_OFS	0xc
17*4882a593Smuzhiyun #define MLB_TMR_REGSZPCH	0x10
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define MLB_TMR_TMCSR_OUTL	BIT(5)
20*4882a593Smuzhiyun #define MLB_TMR_TMCSR_RELD	BIT(4)
21*4882a593Smuzhiyun #define MLB_TMR_TMCSR_INTE	BIT(3)
22*4882a593Smuzhiyun #define MLB_TMR_TMCSR_UF	BIT(2)
23*4882a593Smuzhiyun #define MLB_TMR_TMCSR_CNTE	BIT(1)
24*4882a593Smuzhiyun #define MLB_TMR_TMCSR_TRG	BIT(0)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define MLB_TMR_TMCSR_CSL_DIV2	0
27*4882a593Smuzhiyun #define MLB_TMR_DIV_CNT		2
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define MLB_TMR_SRC_CH		1
30*4882a593Smuzhiyun #define MLB_TMR_EVT_CH		0
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MLB_TMR_SRC_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
33*4882a593Smuzhiyun #define MLB_TMR_EVT_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define MLB_TMR_SRC_TMCSR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
36*4882a593Smuzhiyun #define MLB_TMR_SRC_TMR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
37*4882a593Smuzhiyun #define MLB_TMR_SRC_TMRLR1_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
38*4882a593Smuzhiyun #define MLB_TMR_SRC_TMRLR2_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define MLB_TMR_EVT_TMCSR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
41*4882a593Smuzhiyun #define MLB_TMR_EVT_TMR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
42*4882a593Smuzhiyun #define MLB_TMR_EVT_TMRLR1_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
43*4882a593Smuzhiyun #define MLB_TMR_EVT_TMRLR2_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MLB_TIMER_RATING	500
46*4882a593Smuzhiyun #define MLB_TIMER_ONESHOT	0
47*4882a593Smuzhiyun #define MLB_TIMER_PERIODIC	1
48*4882a593Smuzhiyun 
mlb_timer_interrupt(int irq,void * dev_id)49*4882a593Smuzhiyun static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct clock_event_device *clk = dev_id;
52*4882a593Smuzhiyun 	struct timer_of *to = to_timer_of(clk);
53*4882a593Smuzhiyun 	u32 val;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
56*4882a593Smuzhiyun 	val &= ~MLB_TMR_TMCSR_UF;
57*4882a593Smuzhiyun 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	clk->event_handler(clk);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	return IRQ_HANDLED;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
mlb_evt_timer_start(struct timer_of * to,bool periodic)64*4882a593Smuzhiyun static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
69*4882a593Smuzhiyun 	if (periodic)
70*4882a593Smuzhiyun 		val |= MLB_TMR_TMCSR_RELD;
71*4882a593Smuzhiyun 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
mlb_evt_timer_stop(struct timer_of * to)74*4882a593Smuzhiyun static void mlb_evt_timer_stop(struct timer_of *to)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	val &= ~MLB_TMR_TMCSR_CNTE;
79*4882a593Smuzhiyun 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
mlb_evt_timer_register_count(struct timer_of * to,unsigned long cnt)82*4882a593Smuzhiyun static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long cnt)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
mlb_set_state_periodic(struct clock_event_device * clk)87*4882a593Smuzhiyun static int mlb_set_state_periodic(struct clock_event_device *clk)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct timer_of *to = to_timer_of(clk);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	mlb_evt_timer_stop(to);
92*4882a593Smuzhiyun 	mlb_evt_timer_register_count(to, to->of_clk.period);
93*4882a593Smuzhiyun 	mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
94*4882a593Smuzhiyun 	return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
mlb_set_state_oneshot(struct clock_event_device * clk)97*4882a593Smuzhiyun static int mlb_set_state_oneshot(struct clock_event_device *clk)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct timer_of *to = to_timer_of(clk);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	mlb_evt_timer_stop(to);
102*4882a593Smuzhiyun 	mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
103*4882a593Smuzhiyun 	return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
mlb_set_state_shutdown(struct clock_event_device * clk)106*4882a593Smuzhiyun static int mlb_set_state_shutdown(struct clock_event_device *clk)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	struct timer_of *to = to_timer_of(clk);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	mlb_evt_timer_stop(to);
111*4882a593Smuzhiyun 	return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
mlb_clkevt_next_event(unsigned long event,struct clock_event_device * clk)114*4882a593Smuzhiyun static int mlb_clkevt_next_event(unsigned long event,
115*4882a593Smuzhiyun 				   struct clock_event_device *clk)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	struct timer_of *to = to_timer_of(clk);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	mlb_evt_timer_stop(to);
120*4882a593Smuzhiyun 	mlb_evt_timer_register_count(to, event);
121*4882a593Smuzhiyun 	mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
122*4882a593Smuzhiyun 	return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
mlb_config_clock_source(struct timer_of * to)125*4882a593Smuzhiyun static int mlb_config_clock_source(struct timer_of *to)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
130*4882a593Smuzhiyun 	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
131*4882a593Smuzhiyun 	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
132*4882a593Smuzhiyun 	val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
133*4882a593Smuzhiyun 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
134*4882a593Smuzhiyun 	return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
mlb_config_clock_event(struct timer_of * to)137*4882a593Smuzhiyun static int mlb_config_clock_event(struct timer_of *to)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static struct timer_of to = {
144*4882a593Smuzhiyun 	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	.clkevt = {
147*4882a593Smuzhiyun 		.name = "mlb-clkevt",
148*4882a593Smuzhiyun 		.rating = MLB_TIMER_RATING,
149*4882a593Smuzhiyun 		.cpumask = cpu_possible_mask,
150*4882a593Smuzhiyun 		.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
151*4882a593Smuzhiyun 		.set_state_oneshot = mlb_set_state_oneshot,
152*4882a593Smuzhiyun 		.set_state_periodic = mlb_set_state_periodic,
153*4882a593Smuzhiyun 		.set_state_shutdown = mlb_set_state_shutdown,
154*4882a593Smuzhiyun 		.set_next_event = mlb_clkevt_next_event,
155*4882a593Smuzhiyun 	},
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	.of_irq = {
158*4882a593Smuzhiyun 		.flags = IRQF_TIMER | IRQF_IRQPOLL,
159*4882a593Smuzhiyun 		.handler = mlb_timer_interrupt,
160*4882a593Smuzhiyun 	},
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
mlb_timer_sched_read(void)163*4882a593Smuzhiyun static u64 notrace mlb_timer_sched_read(void)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
mlb_timer_init(struct device_node * node)168*4882a593Smuzhiyun static int __init mlb_timer_init(struct device_node *node)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	int ret;
171*4882a593Smuzhiyun 	unsigned long rate;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	ret = timer_of_init(node, &to);
174*4882a593Smuzhiyun 	if (ret)
175*4882a593Smuzhiyun 		return ret;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
178*4882a593Smuzhiyun 	mlb_config_clock_source(&to);
179*4882a593Smuzhiyun 	clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
180*4882a593Smuzhiyun 		node->name, rate, MLB_TIMER_RATING, 32,
181*4882a593Smuzhiyun 		clocksource_mmio_readl_down);
182*4882a593Smuzhiyun 	sched_clock_register(mlb_timer_sched_read, 32, rate);
183*4882a593Smuzhiyun 	mlb_config_clock_event(&to);
184*4882a593Smuzhiyun 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
185*4882a593Smuzhiyun 		0xffffffff);
186*4882a593Smuzhiyun 	return 0;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
189*4882a593Smuzhiyun 		mlb_timer_init);
190