xref: /OK3568_Linux_fs/kernel/drivers/clocksource/em_sti.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Emma Mobile Timer Support - STI
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2012 Magnus Damm
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/spinlock.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/ioport.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/clocksource.h>
19*4882a593Smuzhiyun #include <linux/clockchips.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun enum { USER_CLOCKSOURCE, USER_CLOCKEVENT, USER_NR };
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct em_sti_priv {
26*4882a593Smuzhiyun 	void __iomem *base;
27*4882a593Smuzhiyun 	struct clk *clk;
28*4882a593Smuzhiyun 	struct platform_device *pdev;
29*4882a593Smuzhiyun 	unsigned int active[USER_NR];
30*4882a593Smuzhiyun 	unsigned long rate;
31*4882a593Smuzhiyun 	raw_spinlock_t lock;
32*4882a593Smuzhiyun 	struct clock_event_device ced;
33*4882a593Smuzhiyun 	struct clocksource cs;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define STI_CONTROL 0x00
37*4882a593Smuzhiyun #define STI_COMPA_H 0x10
38*4882a593Smuzhiyun #define STI_COMPA_L 0x14
39*4882a593Smuzhiyun #define STI_COMPB_H 0x18
40*4882a593Smuzhiyun #define STI_COMPB_L 0x1c
41*4882a593Smuzhiyun #define STI_COUNT_H 0x20
42*4882a593Smuzhiyun #define STI_COUNT_L 0x24
43*4882a593Smuzhiyun #define STI_COUNT_RAW_H 0x28
44*4882a593Smuzhiyun #define STI_COUNT_RAW_L 0x2c
45*4882a593Smuzhiyun #define STI_SET_H 0x30
46*4882a593Smuzhiyun #define STI_SET_L 0x34
47*4882a593Smuzhiyun #define STI_INTSTATUS 0x40
48*4882a593Smuzhiyun #define STI_INTRAWSTATUS 0x44
49*4882a593Smuzhiyun #define STI_INTENSET 0x48
50*4882a593Smuzhiyun #define STI_INTENCLR 0x4c
51*4882a593Smuzhiyun #define STI_INTFFCLR 0x50
52*4882a593Smuzhiyun 
em_sti_read(struct em_sti_priv * p,int offs)53*4882a593Smuzhiyun static inline unsigned long em_sti_read(struct em_sti_priv *p, int offs)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	return ioread32(p->base + offs);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
em_sti_write(struct em_sti_priv * p,int offs,unsigned long value)58*4882a593Smuzhiyun static inline void em_sti_write(struct em_sti_priv *p, int offs,
59*4882a593Smuzhiyun 				unsigned long value)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	iowrite32(value, p->base + offs);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
em_sti_enable(struct em_sti_priv * p)64*4882a593Smuzhiyun static int em_sti_enable(struct em_sti_priv *p)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	int ret;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	/* enable clock */
69*4882a593Smuzhiyun 	ret = clk_enable(p->clk);
70*4882a593Smuzhiyun 	if (ret) {
71*4882a593Smuzhiyun 		dev_err(&p->pdev->dev, "cannot enable clock\n");
72*4882a593Smuzhiyun 		return ret;
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	/* reset the counter */
76*4882a593Smuzhiyun 	em_sti_write(p, STI_SET_H, 0x40000000);
77*4882a593Smuzhiyun 	em_sti_write(p, STI_SET_L, 0x00000000);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* mask and clear pending interrupts */
80*4882a593Smuzhiyun 	em_sti_write(p, STI_INTENCLR, 3);
81*4882a593Smuzhiyun 	em_sti_write(p, STI_INTFFCLR, 3);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/* enable updates of counter registers */
84*4882a593Smuzhiyun 	em_sti_write(p, STI_CONTROL, 1);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
em_sti_disable(struct em_sti_priv * p)89*4882a593Smuzhiyun static void em_sti_disable(struct em_sti_priv *p)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	/* mask interrupts */
92*4882a593Smuzhiyun 	em_sti_write(p, STI_INTENCLR, 3);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* stop clock */
95*4882a593Smuzhiyun 	clk_disable(p->clk);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun 
em_sti_count(struct em_sti_priv * p)98*4882a593Smuzhiyun static u64 em_sti_count(struct em_sti_priv *p)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	u64 ticks;
101*4882a593Smuzhiyun 	unsigned long flags;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	/* the STI hardware buffers the 48-bit count, but to
104*4882a593Smuzhiyun 	 * break it out into two 32-bit access the registers
105*4882a593Smuzhiyun 	 * must be accessed in a certain order.
106*4882a593Smuzhiyun 	 * Always read STI_COUNT_H before STI_COUNT_L.
107*4882a593Smuzhiyun 	 */
108*4882a593Smuzhiyun 	raw_spin_lock_irqsave(&p->lock, flags);
109*4882a593Smuzhiyun 	ticks = (u64)(em_sti_read(p, STI_COUNT_H) & 0xffff) << 32;
110*4882a593Smuzhiyun 	ticks |= em_sti_read(p, STI_COUNT_L);
111*4882a593Smuzhiyun 	raw_spin_unlock_irqrestore(&p->lock, flags);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	return ticks;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
em_sti_set_next(struct em_sti_priv * p,u64 next)116*4882a593Smuzhiyun static u64 em_sti_set_next(struct em_sti_priv *p, u64 next)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	unsigned long flags;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	raw_spin_lock_irqsave(&p->lock, flags);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* mask compare A interrupt */
123*4882a593Smuzhiyun 	em_sti_write(p, STI_INTENCLR, 1);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* update compare A value */
126*4882a593Smuzhiyun 	em_sti_write(p, STI_COMPA_H, next >> 32);
127*4882a593Smuzhiyun 	em_sti_write(p, STI_COMPA_L, next & 0xffffffff);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* clear compare A interrupt source */
130*4882a593Smuzhiyun 	em_sti_write(p, STI_INTFFCLR, 1);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	/* unmask compare A interrupt */
133*4882a593Smuzhiyun 	em_sti_write(p, STI_INTENSET, 1);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	raw_spin_unlock_irqrestore(&p->lock, flags);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return next;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
em_sti_interrupt(int irq,void * dev_id)140*4882a593Smuzhiyun static irqreturn_t em_sti_interrupt(int irq, void *dev_id)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct em_sti_priv *p = dev_id;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	p->ced.event_handler(&p->ced);
145*4882a593Smuzhiyun 	return IRQ_HANDLED;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
em_sti_start(struct em_sti_priv * p,unsigned int user)148*4882a593Smuzhiyun static int em_sti_start(struct em_sti_priv *p, unsigned int user)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	unsigned long flags;
151*4882a593Smuzhiyun 	int used_before;
152*4882a593Smuzhiyun 	int ret = 0;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	raw_spin_lock_irqsave(&p->lock, flags);
155*4882a593Smuzhiyun 	used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
156*4882a593Smuzhiyun 	if (!used_before)
157*4882a593Smuzhiyun 		ret = em_sti_enable(p);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (!ret)
160*4882a593Smuzhiyun 		p->active[user] = 1;
161*4882a593Smuzhiyun 	raw_spin_unlock_irqrestore(&p->lock, flags);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return ret;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
em_sti_stop(struct em_sti_priv * p,unsigned int user)166*4882a593Smuzhiyun static void em_sti_stop(struct em_sti_priv *p, unsigned int user)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	unsigned long flags;
169*4882a593Smuzhiyun 	int used_before, used_after;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	raw_spin_lock_irqsave(&p->lock, flags);
172*4882a593Smuzhiyun 	used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
173*4882a593Smuzhiyun 	p->active[user] = 0;
174*4882a593Smuzhiyun 	used_after = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	if (used_before && !used_after)
177*4882a593Smuzhiyun 		em_sti_disable(p);
178*4882a593Smuzhiyun 	raw_spin_unlock_irqrestore(&p->lock, flags);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
cs_to_em_sti(struct clocksource * cs)181*4882a593Smuzhiyun static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	return container_of(cs, struct em_sti_priv, cs);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
em_sti_clocksource_read(struct clocksource * cs)186*4882a593Smuzhiyun static u64 em_sti_clocksource_read(struct clocksource *cs)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	return em_sti_count(cs_to_em_sti(cs));
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
em_sti_clocksource_enable(struct clocksource * cs)191*4882a593Smuzhiyun static int em_sti_clocksource_enable(struct clocksource *cs)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct em_sti_priv *p = cs_to_em_sti(cs);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	return em_sti_start(p, USER_CLOCKSOURCE);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
em_sti_clocksource_disable(struct clocksource * cs)198*4882a593Smuzhiyun static void em_sti_clocksource_disable(struct clocksource *cs)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun 
em_sti_clocksource_resume(struct clocksource * cs)203*4882a593Smuzhiyun static void em_sti_clocksource_resume(struct clocksource *cs)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun 	em_sti_clocksource_enable(cs);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
em_sti_register_clocksource(struct em_sti_priv * p)208*4882a593Smuzhiyun static int em_sti_register_clocksource(struct em_sti_priv *p)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct clocksource *cs = &p->cs;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	cs->name = dev_name(&p->pdev->dev);
213*4882a593Smuzhiyun 	cs->rating = 200;
214*4882a593Smuzhiyun 	cs->read = em_sti_clocksource_read;
215*4882a593Smuzhiyun 	cs->enable = em_sti_clocksource_enable;
216*4882a593Smuzhiyun 	cs->disable = em_sti_clocksource_disable;
217*4882a593Smuzhiyun 	cs->suspend = em_sti_clocksource_disable;
218*4882a593Smuzhiyun 	cs->resume = em_sti_clocksource_resume;
219*4882a593Smuzhiyun 	cs->mask = CLOCKSOURCE_MASK(48);
220*4882a593Smuzhiyun 	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	dev_info(&p->pdev->dev, "used as clock source\n");
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	clocksource_register_hz(cs, p->rate);
225*4882a593Smuzhiyun 	return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
ced_to_em_sti(struct clock_event_device * ced)228*4882a593Smuzhiyun static struct em_sti_priv *ced_to_em_sti(struct clock_event_device *ced)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	return container_of(ced, struct em_sti_priv, ced);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
em_sti_clock_event_shutdown(struct clock_event_device * ced)233*4882a593Smuzhiyun static int em_sti_clock_event_shutdown(struct clock_event_device *ced)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct em_sti_priv *p = ced_to_em_sti(ced);
236*4882a593Smuzhiyun 	em_sti_stop(p, USER_CLOCKEVENT);
237*4882a593Smuzhiyun 	return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
em_sti_clock_event_set_oneshot(struct clock_event_device * ced)240*4882a593Smuzhiyun static int em_sti_clock_event_set_oneshot(struct clock_event_device *ced)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	struct em_sti_priv *p = ced_to_em_sti(ced);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	dev_info(&p->pdev->dev, "used for oneshot clock events\n");
245*4882a593Smuzhiyun 	em_sti_start(p, USER_CLOCKEVENT);
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
em_sti_clock_event_next(unsigned long delta,struct clock_event_device * ced)249*4882a593Smuzhiyun static int em_sti_clock_event_next(unsigned long delta,
250*4882a593Smuzhiyun 				   struct clock_event_device *ced)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	struct em_sti_priv *p = ced_to_em_sti(ced);
253*4882a593Smuzhiyun 	u64 next;
254*4882a593Smuzhiyun 	int safe;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	next = em_sti_set_next(p, em_sti_count(p) + delta);
257*4882a593Smuzhiyun 	safe = em_sti_count(p) < (next - 1);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	return !safe;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
em_sti_register_clockevent(struct em_sti_priv * p)262*4882a593Smuzhiyun static void em_sti_register_clockevent(struct em_sti_priv *p)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	struct clock_event_device *ced = &p->ced;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	ced->name = dev_name(&p->pdev->dev);
267*4882a593Smuzhiyun 	ced->features = CLOCK_EVT_FEAT_ONESHOT;
268*4882a593Smuzhiyun 	ced->rating = 200;
269*4882a593Smuzhiyun 	ced->cpumask = cpu_possible_mask;
270*4882a593Smuzhiyun 	ced->set_next_event = em_sti_clock_event_next;
271*4882a593Smuzhiyun 	ced->set_state_shutdown = em_sti_clock_event_shutdown;
272*4882a593Smuzhiyun 	ced->set_state_oneshot = em_sti_clock_event_set_oneshot;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	dev_info(&p->pdev->dev, "used for clock events\n");
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	clockevents_config_and_register(ced, p->rate, 2, 0xffffffff);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun 
em_sti_probe(struct platform_device * pdev)279*4882a593Smuzhiyun static int em_sti_probe(struct platform_device *pdev)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun 	struct em_sti_priv *p;
282*4882a593Smuzhiyun 	int irq, ret;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
285*4882a593Smuzhiyun 	if (p == NULL)
286*4882a593Smuzhiyun 		return -ENOMEM;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	p->pdev = pdev;
289*4882a593Smuzhiyun 	platform_set_drvdata(pdev, p);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
292*4882a593Smuzhiyun 	if (irq < 0)
293*4882a593Smuzhiyun 		return irq;
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	/* map memory, let base point to the STI instance */
296*4882a593Smuzhiyun 	p->base = devm_platform_ioremap_resource(pdev, 0);
297*4882a593Smuzhiyun 	if (IS_ERR(p->base))
298*4882a593Smuzhiyun 		return PTR_ERR(p->base);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, irq, em_sti_interrupt,
301*4882a593Smuzhiyun 			       IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
302*4882a593Smuzhiyun 			       dev_name(&pdev->dev), p);
303*4882a593Smuzhiyun 	if (ret) {
304*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to request low IRQ\n");
305*4882a593Smuzhiyun 		return ret;
306*4882a593Smuzhiyun 	}
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/* get hold of clock */
309*4882a593Smuzhiyun 	p->clk = devm_clk_get(&pdev->dev, "sclk");
310*4882a593Smuzhiyun 	if (IS_ERR(p->clk)) {
311*4882a593Smuzhiyun 		dev_err(&pdev->dev, "cannot get clock\n");
312*4882a593Smuzhiyun 		return PTR_ERR(p->clk);
313*4882a593Smuzhiyun 	}
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	ret = clk_prepare(p->clk);
316*4882a593Smuzhiyun 	if (ret < 0) {
317*4882a593Smuzhiyun 		dev_err(&pdev->dev, "cannot prepare clock\n");
318*4882a593Smuzhiyun 		return ret;
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	ret = clk_enable(p->clk);
322*4882a593Smuzhiyun 	if (ret < 0) {
323*4882a593Smuzhiyun 		dev_err(&p->pdev->dev, "cannot enable clock\n");
324*4882a593Smuzhiyun 		clk_unprepare(p->clk);
325*4882a593Smuzhiyun 		return ret;
326*4882a593Smuzhiyun 	}
327*4882a593Smuzhiyun 	p->rate = clk_get_rate(p->clk);
328*4882a593Smuzhiyun 	clk_disable(p->clk);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	raw_spin_lock_init(&p->lock);
331*4882a593Smuzhiyun 	em_sti_register_clockevent(p);
332*4882a593Smuzhiyun 	em_sti_register_clocksource(p);
333*4882a593Smuzhiyun 	return 0;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun 
em_sti_remove(struct platform_device * pdev)336*4882a593Smuzhiyun static int em_sti_remove(struct platform_device *pdev)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun 	return -EBUSY; /* cannot unregister clockevent and clocksource */
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun static const struct of_device_id em_sti_dt_ids[] = {
342*4882a593Smuzhiyun 	{ .compatible = "renesas,em-sti", },
343*4882a593Smuzhiyun 	{},
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, em_sti_dt_ids);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static struct platform_driver em_sti_device_driver = {
348*4882a593Smuzhiyun 	.probe		= em_sti_probe,
349*4882a593Smuzhiyun 	.remove		= em_sti_remove,
350*4882a593Smuzhiyun 	.driver		= {
351*4882a593Smuzhiyun 		.name	= "em_sti",
352*4882a593Smuzhiyun 		.of_match_table = em_sti_dt_ids,
353*4882a593Smuzhiyun 	}
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
em_sti_init(void)356*4882a593Smuzhiyun static int __init em_sti_init(void)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	return platform_driver_register(&em_sti_device_driver);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
em_sti_exit(void)361*4882a593Smuzhiyun static void __exit em_sti_exit(void)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	platform_driver_unregister(&em_sti_device_driver);
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun subsys_initcall(em_sti_init);
367*4882a593Smuzhiyun module_exit(em_sti_exit);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun MODULE_AUTHOR("Magnus Damm");
370*4882a593Smuzhiyun MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
371*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
372