1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2011
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6*4882a593Smuzhiyun * Author: Sundar Iyer for ST-Ericsson
7*4882a593Smuzhiyun * sched_clock implementation is based on:
8*4882a593Smuzhiyun * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * DBx500-PRCMU Timer
11*4882a593Smuzhiyun * The PRCMU has 5 timers which are available in a always-on
12*4882a593Smuzhiyun * power domain. We use the Timer 4 for our always-on clock
13*4882a593Smuzhiyun * source on DB8500.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_address.h>
17*4882a593Smuzhiyun #include <linux/clockchips.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define RATE_32K 32768
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define TIMER_MODE_CONTINOUS 0x1
22*4882a593Smuzhiyun #define TIMER_DOWNCOUNT_VAL 0xffffffff
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define PRCMU_TIMER_REF 0
25*4882a593Smuzhiyun #define PRCMU_TIMER_DOWNCOUNT 0x4
26*4882a593Smuzhiyun #define PRCMU_TIMER_MODE 0x8
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static void __iomem *clksrc_dbx500_timer_base;
29*4882a593Smuzhiyun
clksrc_dbx500_prcmu_read(struct clocksource * cs)30*4882a593Smuzhiyun static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun void __iomem *base = clksrc_dbx500_timer_base;
33*4882a593Smuzhiyun u32 count, count2;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun do {
36*4882a593Smuzhiyun count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
37*4882a593Smuzhiyun count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
38*4882a593Smuzhiyun } while (count2 != count);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Negate because the timer is a decrementing counter */
41*4882a593Smuzhiyun return ~count;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static struct clocksource clocksource_dbx500_prcmu = {
45*4882a593Smuzhiyun .name = "dbx500-prcmu-timer",
46*4882a593Smuzhiyun .rating = 100,
47*4882a593Smuzhiyun .read = clksrc_dbx500_prcmu_read,
48*4882a593Smuzhiyun .mask = CLOCKSOURCE_MASK(32),
49*4882a593Smuzhiyun .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
clksrc_dbx500_prcmu_init(struct device_node * node)52*4882a593Smuzhiyun static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun clksrc_dbx500_timer_base = of_iomap(node, 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * The A9 sub system expects the timer to be configured as
58*4882a593Smuzhiyun * a continous looping timer.
59*4882a593Smuzhiyun * The PRCMU should configure it but if it for some reason
60*4882a593Smuzhiyun * don't we do it here.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
63*4882a593Smuzhiyun TIMER_MODE_CONTINOUS) {
64*4882a593Smuzhiyun writel(TIMER_MODE_CONTINOUS,
65*4882a593Smuzhiyun clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
66*4882a593Smuzhiyun writel(TIMER_DOWNCOUNT_VAL,
67*4882a593Smuzhiyun clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
72*4882a593Smuzhiyun clksrc_dbx500_prcmu_init);
73