1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) Maxime Coquelin 2015
4*4882a593Smuzhiyun * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/clocksource.h>
9*4882a593Smuzhiyun #include <linux/clockchips.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/bitops.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SYST_CSR 0x00
17*4882a593Smuzhiyun #define SYST_RVR 0x04
18*4882a593Smuzhiyun #define SYST_CVR 0x08
19*4882a593Smuzhiyun #define SYST_CALIB 0x0c
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define SYST_CSR_ENABLE BIT(0)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define SYSTICK_LOAD_RELOAD_MASK 0x00FFFFFF
24*4882a593Smuzhiyun
system_timer_of_register(struct device_node * np)25*4882a593Smuzhiyun static int __init system_timer_of_register(struct device_node *np)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct clk *clk = NULL;
28*4882a593Smuzhiyun void __iomem *base;
29*4882a593Smuzhiyun u32 rate;
30*4882a593Smuzhiyun int ret;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun base = of_iomap(np, 0);
33*4882a593Smuzhiyun if (!base) {
34*4882a593Smuzhiyun pr_warn("system-timer: invalid base address\n");
35*4882a593Smuzhiyun return -ENXIO;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun ret = of_property_read_u32(np, "clock-frequency", &rate);
39*4882a593Smuzhiyun if (ret) {
40*4882a593Smuzhiyun clk = of_clk_get(np, 0);
41*4882a593Smuzhiyun if (IS_ERR(clk)) {
42*4882a593Smuzhiyun ret = PTR_ERR(clk);
43*4882a593Smuzhiyun goto out_unmap;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = clk_prepare_enable(clk);
47*4882a593Smuzhiyun if (ret)
48*4882a593Smuzhiyun goto out_clk_put;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun rate = clk_get_rate(clk);
51*4882a593Smuzhiyun if (!rate) {
52*4882a593Smuzhiyun ret = -EINVAL;
53*4882a593Smuzhiyun goto out_clk_disable;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR);
58*4882a593Smuzhiyun writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate,
61*4882a593Smuzhiyun 200, 24, clocksource_mmio_readl_down);
62*4882a593Smuzhiyun if (ret) {
63*4882a593Smuzhiyun pr_err("failed to init clocksource (%d)\n", ret);
64*4882a593Smuzhiyun if (clk)
65*4882a593Smuzhiyun goto out_clk_disable;
66*4882a593Smuzhiyun else
67*4882a593Smuzhiyun goto out_unmap;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun pr_info("ARM System timer initialized as clocksource\n");
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun out_clk_disable:
75*4882a593Smuzhiyun clk_disable_unprepare(clk);
76*4882a593Smuzhiyun out_clk_put:
77*4882a593Smuzhiyun clk_put(clk);
78*4882a593Smuzhiyun out_unmap:
79*4882a593Smuzhiyun iounmap(base);
80*4882a593Smuzhiyun pr_warn("ARM System timer register failed (%d)\n", ret);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun TIMER_OF_DECLARE(arm_systick, "arm,armv7m-systick",
86*4882a593Smuzhiyun system_timer_of_register);
87