1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Clocks for ux500 platforms 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 ST-Ericsson SA 6*4882a593Smuzhiyun * Author: Ulf Hansson <ulf.hansson@linaro.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __UX500_CLK_H 10*4882a593Smuzhiyun #define __UX500_CLK_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/device.h> 13*4882a593Smuzhiyun #include <linux/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct clk; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct clk *clk_reg_prcc_pclk(const char *name, 18*4882a593Smuzhiyun const char *parent_name, 19*4882a593Smuzhiyun resource_size_t phy_base, 20*4882a593Smuzhiyun u32 cg_sel, 21*4882a593Smuzhiyun unsigned long flags); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct clk *clk_reg_prcc_kclk(const char *name, 24*4882a593Smuzhiyun const char *parent_name, 25*4882a593Smuzhiyun resource_size_t phy_base, 26*4882a593Smuzhiyun u32 cg_sel, 27*4882a593Smuzhiyun unsigned long flags); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct clk *clk_reg_prcmu_scalable(const char *name, 30*4882a593Smuzhiyun const char *parent_name, 31*4882a593Smuzhiyun u8 cg_sel, 32*4882a593Smuzhiyun unsigned long rate, 33*4882a593Smuzhiyun unsigned long flags); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct clk *clk_reg_prcmu_gate(const char *name, 36*4882a593Smuzhiyun const char *parent_name, 37*4882a593Smuzhiyun u8 cg_sel, 38*4882a593Smuzhiyun unsigned long flags); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct clk *clk_reg_prcmu_scalable_rate(const char *name, 41*4882a593Smuzhiyun const char *parent_name, 42*4882a593Smuzhiyun u8 cg_sel, 43*4882a593Smuzhiyun unsigned long rate, 44*4882a593Smuzhiyun unsigned long flags); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct clk *clk_reg_prcmu_rate(const char *name, 47*4882a593Smuzhiyun const char *parent_name, 48*4882a593Smuzhiyun u8 cg_sel, 49*4882a593Smuzhiyun unsigned long flags); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct clk *clk_reg_prcmu_opp_gate(const char *name, 52*4882a593Smuzhiyun const char *parent_name, 53*4882a593Smuzhiyun u8 cg_sel, 54*4882a593Smuzhiyun unsigned long flags); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, 57*4882a593Smuzhiyun const char *parent_name, 58*4882a593Smuzhiyun u8 cg_sel, 59*4882a593Smuzhiyun unsigned long rate, 60*4882a593Smuzhiyun unsigned long flags); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct clk *clk_reg_sysctrl_gate(struct device *dev, 63*4882a593Smuzhiyun const char *name, 64*4882a593Smuzhiyun const char *parent_name, 65*4882a593Smuzhiyun u16 reg_sel, 66*4882a593Smuzhiyun u8 reg_mask, 67*4882a593Smuzhiyun u8 reg_bits, 68*4882a593Smuzhiyun unsigned long enable_delay_us, 69*4882a593Smuzhiyun unsigned long flags); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, 72*4882a593Smuzhiyun const char *name, 73*4882a593Smuzhiyun const char *parent_name, 74*4882a593Smuzhiyun u16 reg_sel, 75*4882a593Smuzhiyun u8 reg_mask, 76*4882a593Smuzhiyun u8 reg_bits, 77*4882a593Smuzhiyun unsigned long rate, 78*4882a593Smuzhiyun unsigned long enable_delay_us, 79*4882a593Smuzhiyun unsigned long flags); 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct clk *clk_reg_sysctrl_set_parent(struct device *dev, 82*4882a593Smuzhiyun const char *name, 83*4882a593Smuzhiyun const char **parent_names, 84*4882a593Smuzhiyun u8 num_parents, 85*4882a593Smuzhiyun u16 *reg_sel, 86*4882a593Smuzhiyun u8 *reg_mask, 87*4882a593Smuzhiyun u8 *reg_bits, 88*4882a593Smuzhiyun unsigned long flags); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __UX500_CLK_H */ 91