xref: /OK3568_Linux_fs/kernel/drivers/clk/uniphier/clk-uniphier.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 Socionext Inc.
4*4882a593Smuzhiyun  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __CLK_UNIPHIER_H__
8*4882a593Smuzhiyun #define __CLK_UNIPHIER_H__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun struct clk_hw;
11*4882a593Smuzhiyun struct device;
12*4882a593Smuzhiyun struct regmap;
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS	16
15*4882a593Smuzhiyun #define UNIPHIER_CLK_MUX_MAX_PARENTS		8
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun enum uniphier_clk_type {
18*4882a593Smuzhiyun 	UNIPHIER_CLK_TYPE_CPUGEAR,
19*4882a593Smuzhiyun 	UNIPHIER_CLK_TYPE_FIXED_FACTOR,
20*4882a593Smuzhiyun 	UNIPHIER_CLK_TYPE_FIXED_RATE,
21*4882a593Smuzhiyun 	UNIPHIER_CLK_TYPE_GATE,
22*4882a593Smuzhiyun 	UNIPHIER_CLK_TYPE_MUX,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct uniphier_clk_cpugear_data {
26*4882a593Smuzhiyun 	const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
27*4882a593Smuzhiyun 	unsigned int num_parents;
28*4882a593Smuzhiyun 	unsigned int regbase;
29*4882a593Smuzhiyun 	unsigned int mask;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun struct uniphier_clk_fixed_factor_data {
33*4882a593Smuzhiyun 	const char *parent_name;
34*4882a593Smuzhiyun 	unsigned int mult;
35*4882a593Smuzhiyun 	unsigned int div;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct uniphier_clk_fixed_rate_data {
39*4882a593Smuzhiyun 	unsigned long fixed_rate;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun struct uniphier_clk_gate_data {
43*4882a593Smuzhiyun 	const char *parent_name;
44*4882a593Smuzhiyun 	unsigned int reg;
45*4882a593Smuzhiyun 	unsigned int bit;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct uniphier_clk_mux_data {
49*4882a593Smuzhiyun 	const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
50*4882a593Smuzhiyun 	unsigned int num_parents;
51*4882a593Smuzhiyun 	unsigned int reg;
52*4882a593Smuzhiyun 	unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
53*4882a593Smuzhiyun 	unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun struct uniphier_clk_data {
57*4882a593Smuzhiyun 	const char *name;
58*4882a593Smuzhiyun 	enum uniphier_clk_type type;
59*4882a593Smuzhiyun 	int idx;
60*4882a593Smuzhiyun 	union {
61*4882a593Smuzhiyun 		struct uniphier_clk_cpugear_data cpugear;
62*4882a593Smuzhiyun 		struct uniphier_clk_fixed_factor_data factor;
63*4882a593Smuzhiyun 		struct uniphier_clk_fixed_rate_data rate;
64*4882a593Smuzhiyun 		struct uniphier_clk_gate_data gate;
65*4882a593Smuzhiyun 		struct uniphier_clk_mux_data mux;
66*4882a593Smuzhiyun 	} data;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask,	\
70*4882a593Smuzhiyun 			     _num_parents, ...)			\
71*4882a593Smuzhiyun 	{							\
72*4882a593Smuzhiyun 		.name = (_name),				\
73*4882a593Smuzhiyun 		.type = UNIPHIER_CLK_TYPE_CPUGEAR,		\
74*4882a593Smuzhiyun 		.idx = (_idx),					\
75*4882a593Smuzhiyun 		.data.cpugear = {				\
76*4882a593Smuzhiyun 			.parent_names = { __VA_ARGS__ },	\
77*4882a593Smuzhiyun 			.num_parents = (_num_parents),		\
78*4882a593Smuzhiyun 			.regbase = (_regbase),			\
79*4882a593Smuzhiyun 			.mask = (_mask)				\
80*4882a593Smuzhiyun 		 },						\
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div)	\
84*4882a593Smuzhiyun 	{							\
85*4882a593Smuzhiyun 		.name = (_name),				\
86*4882a593Smuzhiyun 		.type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,		\
87*4882a593Smuzhiyun 		.idx = (_idx),					\
88*4882a593Smuzhiyun 		.data.factor = {				\
89*4882a593Smuzhiyun 			.parent_name = (_parent),		\
90*4882a593Smuzhiyun 			.mult = (_mult),			\
91*4882a593Smuzhiyun 			.div = (_div),				\
92*4882a593Smuzhiyun 		},						\
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit)	\
96*4882a593Smuzhiyun 	{							\
97*4882a593Smuzhiyun 		.name = (_name),				\
98*4882a593Smuzhiyun 		.type = UNIPHIER_CLK_TYPE_GATE,			\
99*4882a593Smuzhiyun 		.idx = (_idx),					\
100*4882a593Smuzhiyun 		.data.gate = {					\
101*4882a593Smuzhiyun 			.parent_name = (_parent),		\
102*4882a593Smuzhiyun 			.reg = (_reg),				\
103*4882a593Smuzhiyun 			.bit = (_bit),				\
104*4882a593Smuzhiyun 		},						\
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define UNIPHIER_CLK_DIV(parent, div)				\
108*4882a593Smuzhiyun 	UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define UNIPHIER_CLK_DIV2(parent, div0, div1)			\
111*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV(parent, div0),				\
112*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV(parent, div1)
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2)		\
115*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV2(parent, div0, div1),			\
116*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV(parent, div2)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3)	\
119*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV2(parent, div0, div1),			\
120*4882a593Smuzhiyun 	UNIPHIER_CLK_DIV2(parent, div2, div3)
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
123*4882a593Smuzhiyun 					     struct regmap *regmap,
124*4882a593Smuzhiyun 					     const char *name,
125*4882a593Smuzhiyun 				const struct uniphier_clk_cpugear_data *data);
126*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
127*4882a593Smuzhiyun 						  const char *name,
128*4882a593Smuzhiyun 			const struct uniphier_clk_fixed_factor_data *data);
129*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
130*4882a593Smuzhiyun 						const char *name,
131*4882a593Smuzhiyun 			const struct uniphier_clk_fixed_rate_data *data);
132*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_gate(struct device *dev,
133*4882a593Smuzhiyun 					  struct regmap *regmap,
134*4882a593Smuzhiyun 					  const char *name,
135*4882a593Smuzhiyun 				const struct uniphier_clk_gate_data *data);
136*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_mux(struct device *dev,
137*4882a593Smuzhiyun 					 struct regmap *regmap,
138*4882a593Smuzhiyun 					 const char *name,
139*4882a593Smuzhiyun 				const struct uniphier_clk_mux_data *data);
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
142*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
143*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
144*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
145*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
146*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
147*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
148*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
149*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
150*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
151*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
152*4882a593Smuzhiyun extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #endif /* __CLK_UNIPHIER_H__ */
155