1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "clk-uniphier.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct uniphier_clk_mux {
14*4882a593Smuzhiyun struct clk_hw hw;
15*4882a593Smuzhiyun struct regmap *regmap;
16*4882a593Smuzhiyun unsigned int reg;
17*4882a593Smuzhiyun const unsigned int *masks;
18*4882a593Smuzhiyun const unsigned int *vals;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
22*4882a593Smuzhiyun
uniphier_clk_mux_set_parent(struct clk_hw * hw,u8 index)23*4882a593Smuzhiyun static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
28*4882a593Smuzhiyun mux->vals[index]);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
uniphier_clk_mux_get_parent(struct clk_hw * hw)31*4882a593Smuzhiyun static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
34*4882a593Smuzhiyun unsigned int num_parents = clk_hw_get_num_parents(hw);
35*4882a593Smuzhiyun int ret;
36*4882a593Smuzhiyun unsigned int val;
37*4882a593Smuzhiyun unsigned int i;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun ret = regmap_read(mux->regmap, mux->reg, &val);
40*4882a593Smuzhiyun if (ret)
41*4882a593Smuzhiyun return ret;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun for (i = 0; i < num_parents; i++)
44*4882a593Smuzhiyun if ((mux->masks[i] & val) == mux->vals[i])
45*4882a593Smuzhiyun return i;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return -EINVAL;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct clk_ops uniphier_clk_mux_ops = {
51*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate,
52*4882a593Smuzhiyun .set_parent = uniphier_clk_mux_set_parent,
53*4882a593Smuzhiyun .get_parent = uniphier_clk_mux_get_parent,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
uniphier_clk_register_mux(struct device * dev,struct regmap * regmap,const char * name,const struct uniphier_clk_mux_data * data)56*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_mux(struct device *dev,
57*4882a593Smuzhiyun struct regmap *regmap,
58*4882a593Smuzhiyun const char *name,
59*4882a593Smuzhiyun const struct uniphier_clk_mux_data *data)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct uniphier_clk_mux *mux;
62*4882a593Smuzhiyun struct clk_init_data init;
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
66*4882a593Smuzhiyun if (!mux)
67*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun init.name = name;
70*4882a593Smuzhiyun init.ops = &uniphier_clk_mux_ops;
71*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
72*4882a593Smuzhiyun init.parent_names = data->parent_names;
73*4882a593Smuzhiyun init.num_parents = data->num_parents;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun mux->regmap = regmap;
76*4882a593Smuzhiyun mux->reg = data->reg;
77*4882a593Smuzhiyun mux->masks = data->masks;
78*4882a593Smuzhiyun mux->vals = data->vals;
79*4882a593Smuzhiyun mux->hw.init = &init;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = devm_clk_hw_register(dev, &mux->hw);
82*4882a593Smuzhiyun if (ret)
83*4882a593Smuzhiyun return ERR_PTR(ret);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return &mux->hw;
86*4882a593Smuzhiyun }
87