xref: /OK3568_Linux_fs/kernel/drivers/clk/uniphier/clk-uniphier-gate.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 Socionext Inc.
4*4882a593Smuzhiyun  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include "clk-uniphier.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct uniphier_clk_gate {
14*4882a593Smuzhiyun 	struct clk_hw hw;
15*4882a593Smuzhiyun 	struct regmap *regmap;
16*4882a593Smuzhiyun 	unsigned int reg;
17*4882a593Smuzhiyun 	unsigned int bit;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define to_uniphier_clk_gate(_hw) \
21*4882a593Smuzhiyun 				container_of(_hw, struct uniphier_clk_gate, hw)
22*4882a593Smuzhiyun 
uniphier_clk_gate_endisable(struct clk_hw * hw,int enable)23*4882a593Smuzhiyun static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
28*4882a593Smuzhiyun 				 enable ? BIT(gate->bit) : 0);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun 
uniphier_clk_gate_enable(struct clk_hw * hw)31*4882a593Smuzhiyun static int uniphier_clk_gate_enable(struct clk_hw *hw)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun 	return uniphier_clk_gate_endisable(hw, 1);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun 
uniphier_clk_gate_disable(struct clk_hw * hw)36*4882a593Smuzhiyun static void uniphier_clk_gate_disable(struct clk_hw *hw)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	if (uniphier_clk_gate_endisable(hw, 0) < 0)
39*4882a593Smuzhiyun 		pr_warn("failed to disable clk\n");
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun 
uniphier_clk_gate_is_enabled(struct clk_hw * hw)42*4882a593Smuzhiyun static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
45*4882a593Smuzhiyun 	unsigned int val;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	if (regmap_read(gate->regmap, gate->reg, &val) < 0)
48*4882a593Smuzhiyun 		pr_warn("is_enabled() may return wrong result\n");
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	return !!(val & BIT(gate->bit));
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static const struct clk_ops uniphier_clk_gate_ops = {
54*4882a593Smuzhiyun 	.enable = uniphier_clk_gate_enable,
55*4882a593Smuzhiyun 	.disable = uniphier_clk_gate_disable,
56*4882a593Smuzhiyun 	.is_enabled = uniphier_clk_gate_is_enabled,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
uniphier_clk_register_gate(struct device * dev,struct regmap * regmap,const char * name,const struct uniphier_clk_gate_data * data)59*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_gate(struct device *dev,
60*4882a593Smuzhiyun 					  struct regmap *regmap,
61*4882a593Smuzhiyun 					  const char *name,
62*4882a593Smuzhiyun 				const struct uniphier_clk_gate_data *data)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct uniphier_clk_gate *gate;
65*4882a593Smuzhiyun 	struct clk_init_data init;
66*4882a593Smuzhiyun 	int ret;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
69*4882a593Smuzhiyun 	if (!gate)
70*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	init.name = name;
73*4882a593Smuzhiyun 	init.ops = &uniphier_clk_gate_ops;
74*4882a593Smuzhiyun 	init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
75*4882a593Smuzhiyun 	init.parent_names = data->parent_name ? &data->parent_name : NULL;
76*4882a593Smuzhiyun 	init.num_parents = data->parent_name ? 1 : 0;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	gate->regmap = regmap;
79*4882a593Smuzhiyun 	gate->reg = data->reg;
80*4882a593Smuzhiyun 	gate->bit = data->bit;
81*4882a593Smuzhiyun 	gate->hw.init = &init;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	ret = devm_clk_hw_register(dev, &gate->hw);
84*4882a593Smuzhiyun 	if (ret)
85*4882a593Smuzhiyun 		return ERR_PTR(ret);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return &gate->hw;
88*4882a593Smuzhiyun }
89