1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "clk-uniphier.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR_STAT 0 /* status */
14*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR_SET 4 /* set */
15*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR_UPD 8 /* update */
16*4882a593Smuzhiyun #define UNIPHIER_CLK_CPUGEAR_UPD_BIT BIT(0)
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct uniphier_clk_cpugear {
19*4882a593Smuzhiyun struct clk_hw hw;
20*4882a593Smuzhiyun struct regmap *regmap;
21*4882a593Smuzhiyun unsigned int regbase;
22*4882a593Smuzhiyun unsigned int mask;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define to_uniphier_clk_cpugear(_hw) \
26*4882a593Smuzhiyun container_of(_hw, struct uniphier_clk_cpugear, hw)
27*4882a593Smuzhiyun
uniphier_clk_cpugear_set_parent(struct clk_hw * hw,u8 index)28*4882a593Smuzhiyun static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
31*4882a593Smuzhiyun int ret;
32*4882a593Smuzhiyun unsigned int val;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun ret = regmap_write_bits(gear->regmap,
35*4882a593Smuzhiyun gear->regbase + UNIPHIER_CLK_CPUGEAR_SET,
36*4882a593Smuzhiyun gear->mask, index);
37*4882a593Smuzhiyun if (ret)
38*4882a593Smuzhiyun return ret;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ret = regmap_write_bits(gear->regmap,
41*4882a593Smuzhiyun gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
42*4882a593Smuzhiyun UNIPHIER_CLK_CPUGEAR_UPD_BIT,
43*4882a593Smuzhiyun UNIPHIER_CLK_CPUGEAR_UPD_BIT);
44*4882a593Smuzhiyun if (ret)
45*4882a593Smuzhiyun return ret;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return regmap_read_poll_timeout(gear->regmap,
48*4882a593Smuzhiyun gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
49*4882a593Smuzhiyun val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT),
50*4882a593Smuzhiyun 0, 1);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
uniphier_clk_cpugear_get_parent(struct clk_hw * hw)53*4882a593Smuzhiyun static u8 uniphier_clk_cpugear_get_parent(struct clk_hw *hw)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
56*4882a593Smuzhiyun int num_parents = clk_hw_get_num_parents(hw);
57*4882a593Smuzhiyun int ret;
58*4882a593Smuzhiyun unsigned int val;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = regmap_read(gear->regmap,
61*4882a593Smuzhiyun gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val);
62*4882a593Smuzhiyun if (ret)
63*4882a593Smuzhiyun return ret;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun val &= gear->mask;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return val < num_parents ? val : -EINVAL;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct clk_ops uniphier_clk_cpugear_ops = {
71*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate,
72*4882a593Smuzhiyun .set_parent = uniphier_clk_cpugear_set_parent,
73*4882a593Smuzhiyun .get_parent = uniphier_clk_cpugear_get_parent,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
uniphier_clk_register_cpugear(struct device * dev,struct regmap * regmap,const char * name,const struct uniphier_clk_cpugear_data * data)76*4882a593Smuzhiyun struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
77*4882a593Smuzhiyun struct regmap *regmap,
78*4882a593Smuzhiyun const char *name,
79*4882a593Smuzhiyun const struct uniphier_clk_cpugear_data *data)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct uniphier_clk_cpugear *gear;
82*4882a593Smuzhiyun struct clk_init_data init;
83*4882a593Smuzhiyun int ret;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun gear = devm_kzalloc(dev, sizeof(*gear), GFP_KERNEL);
86*4882a593Smuzhiyun if (!gear)
87*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun init.name = name;
90*4882a593Smuzhiyun init.ops = &uniphier_clk_cpugear_ops;
91*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
92*4882a593Smuzhiyun init.parent_names = data->parent_names;
93*4882a593Smuzhiyun init.num_parents = data->num_parents;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun gear->regmap = regmap;
96*4882a593Smuzhiyun gear->regbase = data->regbase;
97*4882a593Smuzhiyun gear->mask = data->mask;
98*4882a593Smuzhiyun gear->hw.init = &init;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = devm_clk_hw_register(dev, &gear->hw);
101*4882a593Smuzhiyun if (ret)
102*4882a593Smuzhiyun return ERR_PTR(ret);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return &gear->hw;
105*4882a593Smuzhiyun }
106