1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * OMAP interface clock support
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Tero Kristo <t-kristo@ti.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
9*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
10*4882a593Smuzhiyun * published by the Free Software Foundation.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
14*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15*4882a593Smuzhiyun * GNU General Public License for more details.
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/clk-provider.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/of_address.h>
22*4882a593Smuzhiyun #include <linux/clk/ti.h>
23*4882a593Smuzhiyun #include "clock.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #undef pr_fmt
26*4882a593Smuzhiyun #define pr_fmt(fmt) "%s: " fmt, __func__
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct clk_ops ti_interface_clk_ops = {
29*4882a593Smuzhiyun .init = &omap2_init_clk_clkdm,
30*4882a593Smuzhiyun .enable = &omap2_dflt_clk_enable,
31*4882a593Smuzhiyun .disable = &omap2_dflt_clk_disable,
32*4882a593Smuzhiyun .is_enabled = &omap2_dflt_clk_is_enabled,
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
_register_interface(struct device * dev,const char * name,const char * parent_name,struct clk_omap_reg * reg,u8 bit_idx,const struct clk_hw_omap_ops * ops)35*4882a593Smuzhiyun static struct clk *_register_interface(struct device *dev, const char *name,
36*4882a593Smuzhiyun const char *parent_name,
37*4882a593Smuzhiyun struct clk_omap_reg *reg, u8 bit_idx,
38*4882a593Smuzhiyun const struct clk_hw_omap_ops *ops)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct clk_init_data init = { NULL };
41*4882a593Smuzhiyun struct clk_hw_omap *clk_hw;
42*4882a593Smuzhiyun struct clk *clk;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
45*4882a593Smuzhiyun if (!clk_hw)
46*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun clk_hw->hw.init = &init;
49*4882a593Smuzhiyun clk_hw->ops = ops;
50*4882a593Smuzhiyun memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
51*4882a593Smuzhiyun clk_hw->enable_bit = bit_idx;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun init.name = name;
54*4882a593Smuzhiyun init.ops = &ti_interface_clk_ops;
55*4882a593Smuzhiyun init.flags = 0;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun init.num_parents = 1;
58*4882a593Smuzhiyun init.parent_names = &parent_name;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (IS_ERR(clk))
63*4882a593Smuzhiyun kfree(clk_hw);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return clk;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
_of_ti_interface_clk_setup(struct device_node * node,const struct clk_hw_omap_ops * ops)68*4882a593Smuzhiyun static void __init _of_ti_interface_clk_setup(struct device_node *node,
69*4882a593Smuzhiyun const struct clk_hw_omap_ops *ops)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct clk *clk;
72*4882a593Smuzhiyun const char *parent_name;
73*4882a593Smuzhiyun struct clk_omap_reg reg;
74*4882a593Smuzhiyun u8 enable_bit = 0;
75*4882a593Smuzhiyun u32 val;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (ti_clk_get_reg_addr(node, 0, ®))
78*4882a593Smuzhiyun return;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (!of_property_read_u32(node, "ti,bit-shift", &val))
81*4882a593Smuzhiyun enable_bit = val;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun parent_name = of_clk_get_parent_name(node, 0);
84*4882a593Smuzhiyun if (!parent_name) {
85*4882a593Smuzhiyun pr_err("%pOFn must have a parent\n", node);
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun clk = _register_interface(NULL, node->name, parent_name, ®,
90*4882a593Smuzhiyun enable_bit, ops);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (!IS_ERR(clk))
93*4882a593Smuzhiyun of_clk_add_provider(node, of_clk_src_simple_get, clk);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
of_ti_interface_clk_setup(struct device_node * node)96*4882a593Smuzhiyun static void __init of_ti_interface_clk_setup(struct device_node *node)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun _of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
101*4882a593Smuzhiyun of_ti_interface_clk_setup);
102*4882a593Smuzhiyun
of_ti_no_wait_interface_clk_setup(struct device_node * node)103*4882a593Smuzhiyun static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun _of_ti_interface_clk_setup(node, &clkhwops_iclk);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
108*4882a593Smuzhiyun of_ti_no_wait_interface_clk_setup);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #ifdef CONFIG_ARCH_OMAP3
of_ti_hsotgusb_interface_clk_setup(struct device_node * node)111*4882a593Smuzhiyun static void __init of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun _of_ti_interface_clk_setup(node,
114*4882a593Smuzhiyun &clkhwops_omap3430es2_iclk_hsotgusb_wait);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
117*4882a593Smuzhiyun of_ti_hsotgusb_interface_clk_setup);
118*4882a593Smuzhiyun
of_ti_dss_interface_clk_setup(struct device_node * node)119*4882a593Smuzhiyun static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun _of_ti_interface_clk_setup(node,
122*4882a593Smuzhiyun &clkhwops_omap3430es2_iclk_dss_usbhost_wait);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
125*4882a593Smuzhiyun of_ti_dss_interface_clk_setup);
126*4882a593Smuzhiyun
of_ti_ssi_interface_clk_setup(struct device_node * node)127*4882a593Smuzhiyun static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun _of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
132*4882a593Smuzhiyun of_ti_ssi_interface_clk_setup);
133*4882a593Smuzhiyun
of_ti_am35xx_interface_clk_setup(struct device_node * node)134*4882a593Smuzhiyun static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun _of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
139*4882a593Smuzhiyun of_ti_am35xx_interface_clk_setup);
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #ifdef CONFIG_SOC_OMAP2430
of_ti_omap2430_interface_clk_setup(struct device_node * node)143*4882a593Smuzhiyun static void __init of_ti_omap2430_interface_clk_setup(struct device_node *node)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun _of_ti_interface_clk_setup(node, &clkhwops_omap2430_i2chs_wait);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun CLK_OF_DECLARE(ti_omap2430_interface_clk, "ti,omap2430-interface-clock",
148*4882a593Smuzhiyun of_ti_omap2430_interface_clk_setup);
149*4882a593Smuzhiyun #endif
150