1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OMAP2/3 interface clock control
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Nokia Corporation
6*4882a593Smuzhiyun * Paul Walmsley
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #undef DEBUG
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/clk/ti.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "clock.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* Register offsets */
18*4882a593Smuzhiyun #define OMAP24XX_CM_FCLKEN2 0x04
19*4882a593Smuzhiyun #define CM_AUTOIDLE 0x30
20*4882a593Smuzhiyun #define CM_ICLKEN 0x10
21*4882a593Smuzhiyun #define CM_IDLEST 0x20
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define OMAP24XX_CM_IDLEST_VAL 0
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Private functions */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* XXX */
omap2_clkt_iclk_allow_idle(struct clk_hw_omap * clk)28*4882a593Smuzhiyun void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u32 v;
31*4882a593Smuzhiyun struct clk_omap_reg r;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun memcpy(&r, &clk->enable_reg, sizeof(r));
34*4882a593Smuzhiyun r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun v = ti_clk_ll_ops->clk_readl(&r);
37*4882a593Smuzhiyun v |= (1 << clk->enable_bit);
38*4882a593Smuzhiyun ti_clk_ll_ops->clk_writel(v, &r);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* XXX */
omap2_clkt_iclk_deny_idle(struct clk_hw_omap * clk)42*4882a593Smuzhiyun void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun u32 v;
45*4882a593Smuzhiyun struct clk_omap_reg r;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun memcpy(&r, &clk->enable_reg, sizeof(r));
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun v = ti_clk_ll_ops->clk_readl(&r);
52*4882a593Smuzhiyun v &= ~(1 << clk->enable_bit);
53*4882a593Smuzhiyun ti_clk_ll_ops->clk_writel(v, &r);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /**
57*4882a593Smuzhiyun * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
58*4882a593Smuzhiyun * @clk: struct clk * being enabled
59*4882a593Smuzhiyun * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
60*4882a593Smuzhiyun * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
61*4882a593Smuzhiyun * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
62*4882a593Smuzhiyun *
63*4882a593Smuzhiyun * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
64*4882a593Smuzhiyun * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
65*4882a593Smuzhiyun * passes back the correct CM_IDLEST register address for I2CHS
66*4882a593Smuzhiyun * modules. No return value.
67*4882a593Smuzhiyun */
omap2430_clk_i2chs_find_idlest(struct clk_hw_omap * clk,struct clk_omap_reg * idlest_reg,u8 * idlest_bit,u8 * idlest_val)68*4882a593Smuzhiyun static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
69*4882a593Smuzhiyun struct clk_omap_reg *idlest_reg,
70*4882a593Smuzhiyun u8 *idlest_bit,
71*4882a593Smuzhiyun u8 *idlest_val)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
74*4882a593Smuzhiyun idlest_reg->offset ^= (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST);
75*4882a593Smuzhiyun *idlest_bit = clk->enable_bit;
76*4882a593Smuzhiyun *idlest_val = OMAP24XX_CM_IDLEST_VAL;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Public data */
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun const struct clk_hw_omap_ops clkhwops_iclk = {
82*4882a593Smuzhiyun .allow_idle = omap2_clkt_iclk_allow_idle,
83*4882a593Smuzhiyun .deny_idle = omap2_clkt_iclk_deny_idle,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun const struct clk_hw_omap_ops clkhwops_iclk_wait = {
87*4882a593Smuzhiyun .allow_idle = omap2_clkt_iclk_allow_idle,
88*4882a593Smuzhiyun .deny_idle = omap2_clkt_iclk_deny_idle,
89*4882a593Smuzhiyun .find_idlest = omap2_clk_dflt_find_idlest,
90*4882a593Smuzhiyun .find_companion = omap2_clk_dflt_find_companion,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* 2430 I2CHS has non-standard IDLEST register */
94*4882a593Smuzhiyun const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
95*4882a593Smuzhiyun .find_idlest = omap2430_clk_i2chs_find_idlest,
96*4882a593Smuzhiyun .find_companion = omap2_clk_dflt_find_companion,
97*4882a593Smuzhiyun };
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