1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunifeq ($(CONFIG_ARCH_OMAP2PLUS), y) 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunobj-y += clk.o autoidle.o clockdomain.o 5*4882a593Smuzhiyunclk-common = dpll.o composite.o divider.o gate.o \ 6*4882a593Smuzhiyun fixed-factor.o mux.o apll.o \ 7*4882a593Smuzhiyun clkt_dpll.o clkt_iclk.o clkt_dflt.o \ 8*4882a593Smuzhiyun clkctrl.o 9*4882a593Smuzhiyunobj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \ 10*4882a593Smuzhiyun clk-33xx-compat.o 11*4882a593Smuzhiyunobj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o 12*4882a593Smuzhiyunobj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 13*4882a593Smuzhiyunobj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ 14*4882a593Smuzhiyun clk-3xxx.o dpll3xxx.o 15*4882a593Smuzhiyunobj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \ 16*4882a593Smuzhiyun dpll3xxx.o dpll44xx.o 17*4882a593Smuzhiyunobj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ 18*4882a593Smuzhiyun dpll3xxx.o dpll44xx.o 19*4882a593Smuzhiyunobj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ 20*4882a593Smuzhiyun clk-dra7-atl.o dpll3xxx.o \ 21*4882a593Smuzhiyun dpll44xx.o clk-7xx-compat.o 22*4882a593Smuzhiyunobj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \ 23*4882a593Smuzhiyun clk-43xx-compat.o 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunendif # CONFIG_ARCH_OMAP2PLUS 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o 28