1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/export.h>
12*4882a593Smuzhiyun #include <linux/clk/tegra.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "clk.h"
15*4882a593Smuzhiyun #include "clk-id.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define OSC_CTRL 0x50
18*4882a593Smuzhiyun #define OSC_CTRL_OSC_FREQ_SHIFT 28
19*4882a593Smuzhiyun #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
20*4882a593Smuzhiyun #define OSC_CTRL_MASK (0x3f2 | \
21*4882a593Smuzhiyun (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static u32 osc_ctrl_ctx;
24*4882a593Smuzhiyun
tegra_osc_clk_init(void __iomem * clk_base,struct tegra_clk * clks,unsigned long * input_freqs,unsigned int num,unsigned int clk_m_div,unsigned long * osc_freq,unsigned long * pll_ref_freq)25*4882a593Smuzhiyun int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
26*4882a593Smuzhiyun unsigned long *input_freqs, unsigned int num,
27*4882a593Smuzhiyun unsigned int clk_m_div, unsigned long *osc_freq,
28*4882a593Smuzhiyun unsigned long *pll_ref_freq)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct clk *clk, *osc;
31*4882a593Smuzhiyun struct clk **dt_clk;
32*4882a593Smuzhiyun u32 val, pll_ref_div;
33*4882a593Smuzhiyun unsigned osc_idx;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun val = readl_relaxed(clk_base + OSC_CTRL);
36*4882a593Smuzhiyun osc_ctrl_ctx = val & OSC_CTRL_MASK;
37*4882a593Smuzhiyun osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (osc_idx < num)
40*4882a593Smuzhiyun *osc_freq = input_freqs[osc_idx];
41*4882a593Smuzhiyun else
42*4882a593Smuzhiyun *osc_freq = 0;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if (!*osc_freq) {
45*4882a593Smuzhiyun WARN_ON(1);
46*4882a593Smuzhiyun return -EINVAL;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
50*4882a593Smuzhiyun if (!dt_clk)
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
54*4882a593Smuzhiyun *dt_clk = osc;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* osc_div2 */
57*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
58*4882a593Smuzhiyun if (dt_clk) {
59*4882a593Smuzhiyun clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
60*4882a593Smuzhiyun 0, 1, 2);
61*4882a593Smuzhiyun *dt_clk = clk;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* osc_div4 */
65*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
66*4882a593Smuzhiyun if (dt_clk) {
67*4882a593Smuzhiyun clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
68*4882a593Smuzhiyun 0, 1, 4);
69*4882a593Smuzhiyun *dt_clk = clk;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
73*4882a593Smuzhiyun if (!dt_clk)
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
77*4882a593Smuzhiyun 0, 1, clk_m_div);
78*4882a593Smuzhiyun *dt_clk = clk;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* pll_ref */
81*4882a593Smuzhiyun val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
82*4882a593Smuzhiyun pll_ref_div = 1 << val;
83*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
84*4882a593Smuzhiyun if (!dt_clk)
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
88*4882a593Smuzhiyun 0, 1, pll_ref_div);
89*4882a593Smuzhiyun *dt_clk = clk;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (pll_ref_freq)
92*4882a593Smuzhiyun *pll_ref_freq = *osc_freq / pll_ref_div;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
tegra_fixed_clk_init(struct tegra_clk * tegra_clks)97*4882a593Smuzhiyun void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct clk *clk;
100*4882a593Smuzhiyun struct clk **dt_clk;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* clk_32k */
103*4882a593Smuzhiyun dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
104*4882a593Smuzhiyun if (dt_clk) {
105*4882a593Smuzhiyun clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
106*4882a593Smuzhiyun *dt_clk = clk;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
tegra_clk_osc_resume(void __iomem * clk_base)110*4882a593Smuzhiyun void tegra_clk_osc_resume(void __iomem *clk_base)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun u32 val;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
115*4882a593Smuzhiyun val |= osc_ctrl_ctx;
116*4882a593Smuzhiyun writel_relaxed(val, clk_base + OSC_CTRL);
117*4882a593Smuzhiyun fence_udelay(2, clk_base);
118*4882a593Smuzhiyun }
119