1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "clk.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define pll_out_enb(p) (BIT(p->enb_bit_idx))
16*4882a593Smuzhiyun #define pll_out_rst(p) (BIT(p->rst_bit_idx))
17*4882a593Smuzhiyun
clk_pll_out_is_enabled(struct clk_hw * hw)18*4882a593Smuzhiyun static int clk_pll_out_is_enabled(struct clk_hw *hw)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
21*4882a593Smuzhiyun u32 val = readl_relaxed(pll_out->reg);
22*4882a593Smuzhiyun int state;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun state = (val & pll_out_enb(pll_out)) ? 1 : 0;
25*4882a593Smuzhiyun if (!(val & (pll_out_rst(pll_out))))
26*4882a593Smuzhiyun state = 0;
27*4882a593Smuzhiyun return state;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
clk_pll_out_enable(struct clk_hw * hw)30*4882a593Smuzhiyun static int clk_pll_out_enable(struct clk_hw *hw)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
33*4882a593Smuzhiyun unsigned long flags = 0;
34*4882a593Smuzhiyun u32 val;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (pll_out->lock)
37*4882a593Smuzhiyun spin_lock_irqsave(pll_out->lock, flags);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun val = readl_relaxed(pll_out->reg);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun writel_relaxed(val, pll_out->reg);
44*4882a593Smuzhiyun udelay(2);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (pll_out->lock)
47*4882a593Smuzhiyun spin_unlock_irqrestore(pll_out->lock, flags);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
clk_pll_out_disable(struct clk_hw * hw)52*4882a593Smuzhiyun static void clk_pll_out_disable(struct clk_hw *hw)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
55*4882a593Smuzhiyun unsigned long flags = 0;
56*4882a593Smuzhiyun u32 val;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (pll_out->lock)
59*4882a593Smuzhiyun spin_lock_irqsave(pll_out->lock, flags);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun val = readl_relaxed(pll_out->reg);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun writel_relaxed(val, pll_out->reg);
66*4882a593Smuzhiyun udelay(2);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (pll_out->lock)
69*4882a593Smuzhiyun spin_unlock_irqrestore(pll_out->lock, flags);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
tegra_clk_pll_out_restore_context(struct clk_hw * hw)72*4882a593Smuzhiyun static void tegra_clk_pll_out_restore_context(struct clk_hw *hw)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun if (!__clk_get_enable_count(hw->clk))
75*4882a593Smuzhiyun clk_pll_out_disable(hw);
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun clk_pll_out_enable(hw);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun const struct clk_ops tegra_clk_pll_out_ops = {
81*4882a593Smuzhiyun .is_enabled = clk_pll_out_is_enabled,
82*4882a593Smuzhiyun .enable = clk_pll_out_enable,
83*4882a593Smuzhiyun .disable = clk_pll_out_disable,
84*4882a593Smuzhiyun .restore_context = tegra_clk_pll_out_restore_context,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
tegra_clk_register_pll_out(const char * name,const char * parent_name,void __iomem * reg,u8 enb_bit_idx,u8 rst_bit_idx,unsigned long flags,u8 pll_out_flags,spinlock_t * lock)87*4882a593Smuzhiyun struct clk *tegra_clk_register_pll_out(const char *name,
88*4882a593Smuzhiyun const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
89*4882a593Smuzhiyun u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
90*4882a593Smuzhiyun spinlock_t *lock)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct tegra_clk_pll_out *pll_out;
93*4882a593Smuzhiyun struct clk *clk;
94*4882a593Smuzhiyun struct clk_init_data init;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
97*4882a593Smuzhiyun if (!pll_out)
98*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun init.name = name;
101*4882a593Smuzhiyun init.ops = &tegra_clk_pll_out_ops;
102*4882a593Smuzhiyun init.parent_names = (parent_name ? &parent_name : NULL);
103*4882a593Smuzhiyun init.num_parents = (parent_name ? 1 : 0);
104*4882a593Smuzhiyun init.flags = flags;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun pll_out->reg = reg;
107*4882a593Smuzhiyun pll_out->enb_bit_idx = enb_bit_idx;
108*4882a593Smuzhiyun pll_out->rst_bit_idx = rst_bit_idx;
109*4882a593Smuzhiyun pll_out->flags = pll_out_flags;
110*4882a593Smuzhiyun pll_out->lock = lock;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Data in .init is copied by clk_register(), so stack variable OK */
113*4882a593Smuzhiyun pll_out->hw.init = &init;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun clk = clk_register(NULL, &pll_out->hw);
116*4882a593Smuzhiyun if (IS_ERR(clk))
117*4882a593Smuzhiyun kfree(pll_out);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return clk;
120*4882a593Smuzhiyun }
121