1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "clk.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static inline struct tegra_clk_periph_fixed *
to_tegra_clk_periph_fixed(struct clk_hw * hw)12*4882a593Smuzhiyun to_tegra_clk_periph_fixed(struct clk_hw *hw)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun return container_of(hw, struct tegra_clk_periph_fixed, hw);
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun
tegra_clk_periph_fixed_is_enabled(struct clk_hw * hw)17*4882a593Smuzhiyun static int tegra_clk_periph_fixed_is_enabled(struct clk_hw *hw)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
20*4882a593Smuzhiyun u32 mask = 1 << (fixed->num % 32), value;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun value = readl(fixed->base + fixed->regs->enb_reg);
23*4882a593Smuzhiyun if (value & mask) {
24*4882a593Smuzhiyun value = readl(fixed->base + fixed->regs->rst_reg);
25*4882a593Smuzhiyun if ((value & mask) == 0)
26*4882a593Smuzhiyun return 1;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
tegra_clk_periph_fixed_enable(struct clk_hw * hw)32*4882a593Smuzhiyun static int tegra_clk_periph_fixed_enable(struct clk_hw *hw)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
35*4882a593Smuzhiyun u32 mask = 1 << (fixed->num % 32);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun writel(mask, fixed->base + fixed->regs->enb_set_reg);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
tegra_clk_periph_fixed_disable(struct clk_hw * hw)42*4882a593Smuzhiyun static void tegra_clk_periph_fixed_disable(struct clk_hw *hw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
45*4882a593Smuzhiyun u32 mask = 1 << (fixed->num % 32);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun writel(mask, fixed->base + fixed->regs->enb_clr_reg);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static unsigned long
tegra_clk_periph_fixed_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)51*4882a593Smuzhiyun tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
52*4882a593Smuzhiyun unsigned long parent_rate)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
55*4882a593Smuzhiyun unsigned long long rate;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun rate = (unsigned long long)parent_rate * fixed->mul;
58*4882a593Smuzhiyun do_div(rate, fixed->div);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return (unsigned long)rate;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct clk_ops tegra_clk_periph_fixed_ops = {
64*4882a593Smuzhiyun .is_enabled = tegra_clk_periph_fixed_is_enabled,
65*4882a593Smuzhiyun .enable = tegra_clk_periph_fixed_enable,
66*4882a593Smuzhiyun .disable = tegra_clk_periph_fixed_disable,
67*4882a593Smuzhiyun .recalc_rate = tegra_clk_periph_fixed_recalc_rate,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
tegra_clk_register_periph_fixed(const char * name,const char * parent,unsigned long flags,void __iomem * base,unsigned int mul,unsigned int div,unsigned int num)70*4882a593Smuzhiyun struct clk *tegra_clk_register_periph_fixed(const char *name,
71*4882a593Smuzhiyun const char *parent,
72*4882a593Smuzhiyun unsigned long flags,
73*4882a593Smuzhiyun void __iomem *base,
74*4882a593Smuzhiyun unsigned int mul,
75*4882a593Smuzhiyun unsigned int div,
76*4882a593Smuzhiyun unsigned int num)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun const struct tegra_clk_periph_regs *regs;
79*4882a593Smuzhiyun struct tegra_clk_periph_fixed *fixed;
80*4882a593Smuzhiyun struct clk_init_data init;
81*4882a593Smuzhiyun struct clk *clk;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun regs = get_reg_bank(num);
84*4882a593Smuzhiyun if (!regs)
85*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
88*4882a593Smuzhiyun if (!fixed)
89*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun init.name = name;
92*4882a593Smuzhiyun init.flags = flags;
93*4882a593Smuzhiyun init.parent_names = parent ? &parent : NULL;
94*4882a593Smuzhiyun init.num_parents = parent ? 1 : 0;
95*4882a593Smuzhiyun init.ops = &tegra_clk_periph_fixed_ops;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun fixed->base = base;
98*4882a593Smuzhiyun fixed->regs = regs;
99*4882a593Smuzhiyun fixed->mul = mul;
100*4882a593Smuzhiyun fixed->div = div;
101*4882a593Smuzhiyun fixed->num = num;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun fixed->hw.init = &init;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun clk = clk_register(NULL, &fixed->hw);
106*4882a593Smuzhiyun if (IS_ERR(clk))
107*4882a593Smuzhiyun kfree(fixed);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return clk;
110*4882a593Smuzhiyun }
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