1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver 4*4882a593Smuzhiyun * Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Aleksandr Frid <afrid@nvidia.com> 7*4882a593Smuzhiyun * Paul Walmsley <pwalmsley@nvidia.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H 11*4882a593Smuzhiyun #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/platform_device.h> 14*4882a593Smuzhiyun #include <linux/reset.h> 15*4882a593Smuzhiyun #include <linux/types.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "cvb.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /** 20*4882a593Smuzhiyun * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver 21*4882a593Smuzhiyun * @dev: struct device * that holds the OPP table for the DFLL 22*4882a593Smuzhiyun * @max_freq: maximum frequency supported on this SoC 23*4882a593Smuzhiyun * @cvb: CPU frequency table for this SoC 24*4882a593Smuzhiyun * @alignment: parameters of the regulator step and offset 25*4882a593Smuzhiyun * @init_clock_trimmers: callback to initialize clock trimmers 26*4882a593Smuzhiyun * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage 27*4882a593Smuzhiyun * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun struct tegra_dfll_soc_data { 30*4882a593Smuzhiyun struct device *dev; 31*4882a593Smuzhiyun unsigned long max_freq; 32*4882a593Smuzhiyun const struct cvb_table *cvb; 33*4882a593Smuzhiyun struct rail_alignment alignment; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun void (*init_clock_trimmers)(void); 36*4882a593Smuzhiyun void (*set_clock_trimmers_high)(void); 37*4882a593Smuzhiyun void (*set_clock_trimmers_low)(void); 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun int tegra_dfll_register(struct platform_device *pdev, 41*4882a593Smuzhiyun struct tegra_dfll_soc_data *soc); 42*4882a593Smuzhiyun struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev); 43*4882a593Smuzhiyun int tegra_dfll_runtime_suspend(struct device *dev); 44*4882a593Smuzhiyun int tegra_dfll_runtime_resume(struct device *dev); 45*4882a593Smuzhiyun int tegra_dfll_suspend(struct device *dev); 46*4882a593Smuzhiyun int tegra_dfll_resume(struct device *dev); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ 49