1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Free Electrons
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Allwinner A31 APB0 clock driver
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * The APB0 clk has a configurable divisor.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * We must use a clk_div_table and not a regular power of 2
19*4882a593Smuzhiyun * divisor here, because the first 2 values divide the clock
20*4882a593Smuzhiyun * by 2.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun static const struct clk_div_table sun6i_a31_apb0_divs[] = {
23*4882a593Smuzhiyun { .val = 0, .div = 2, },
24*4882a593Smuzhiyun { .val = 1, .div = 2, },
25*4882a593Smuzhiyun { .val = 2, .div = 4, },
26*4882a593Smuzhiyun { .val = 3, .div = 8, },
27*4882a593Smuzhiyun { /* sentinel */ },
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
sun6i_a31_apb0_clk_probe(struct platform_device * pdev)30*4882a593Smuzhiyun static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
33*4882a593Smuzhiyun const char *clk_name = np->name;
34*4882a593Smuzhiyun const char *clk_parent;
35*4882a593Smuzhiyun struct resource *r;
36*4882a593Smuzhiyun void __iomem *reg;
37*4882a593Smuzhiyun struct clk *clk;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
40*4882a593Smuzhiyun reg = devm_ioremap_resource(&pdev->dev, r);
41*4882a593Smuzhiyun if (IS_ERR(reg))
42*4882a593Smuzhiyun return PTR_ERR(reg);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun clk_parent = of_clk_get_parent_name(np, 0);
45*4882a593Smuzhiyun if (!clk_parent)
46*4882a593Smuzhiyun return -EINVAL;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun of_property_read_string(np, "clock-output-names", &clk_name);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
51*4882a593Smuzhiyun 0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
52*4882a593Smuzhiyun NULL);
53*4882a593Smuzhiyun if (IS_ERR(clk))
54*4882a593Smuzhiyun return PTR_ERR(clk);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return of_clk_add_provider(np, of_clk_src_simple_get, clk);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
60*4882a593Smuzhiyun { .compatible = "allwinner,sun6i-a31-apb0-clk" },
61*4882a593Smuzhiyun { /* sentinel */ }
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static struct platform_driver sun6i_a31_apb0_clk_driver = {
65*4882a593Smuzhiyun .driver = {
66*4882a593Smuzhiyun .name = "sun6i-a31-apb0-clk",
67*4882a593Smuzhiyun .of_match_table = sun6i_a31_apb0_clk_dt_ids,
68*4882a593Smuzhiyun },
69*4882a593Smuzhiyun .probe = sun6i_a31_apb0_clk_probe,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun builtin_platform_driver(sun6i_a31_apb0_clk_driver);
72